DFT Engineer

Company Description Mueon Corporation is driven by the vision of delivering “The Next Exponential” in technology innovation, focusing on high-impact solutions that push the boundaries of performance and scalability. The company fosters a culture of rigorous engineering, continuous learning, and collaboration across multidisciplinary teams. Team members are encouraged to tackle complex technical challenges and contribute to products that enable the next generation of computing and electronic systems. Mueon values individuals who are motivated to grow with the organization and help shape its long-term technological roadmap.

DFT Engineer:

Role summary

We’re looking for a DFT (Design-for-Test) Engineer to own testability for our ASIC/SoC designs, from RTL through tapeout. You’ll check designs for testability, insert and optimize scan chains, generate ATPG patterns, and get fault coverage to target. You’ll work closely with the RTL, physical design, STA and product/test engineering teams.

Key responsibilities

• Check designs for testability at RTL and gate level. Find and fix DRC violations such as uncontrollable clocks and resets, combinational loops, and non-scannable flops.
• Define the DFT architecture, including scan, compression, test modes, test clocking and on-chip clock controllers (OCC).
• Insert scan chains and scan compression. Balance chain lengths and handle multiple clock domains and lock-up latches.
• Use TetraMAX (TestMAX ATPG) to generate and optimize ATPG patterns for stuck-at, transition delay, path delay and IDDQ faults.
• Analyze fault and test coverage. Debug untestable and undetected faults, and add test points to close coverage gaps.
• Run gate-level simulations of ATPG patterns, both zero-delay and SDF-annotated timing simulations, and debug any mismatches.
• Support STA with test-mode timing constraints (shift and capture modes) and work with physical design on scan chain reordering.
• Implement and verify MBIST, LBIST, JTAG (IEEE 1149.1) and boundary scan, and IEEE 1500/1687 (IJTAG) where needed.
• Support silicon bring-up on ATE, including pattern conversion (STIL/WGL), failure diagnosis and yield analysis.

Required qualifications

• B.S./M.S. in Electrical or Computer Engineering, or a related field.
• 3 years of hands-on DFT experience on ASIC/SoC projects. At least one tapeout is strongly preferred.
• Hands-on experience with Synopsys TetraMAX / TestMAX ATPG: setting up the tool, running DRC, generating patterns, and reporting and analyzing coverage.
• Scan insertion with Synopsys DFT Compiler / TestMAX DFT, or similar tools.
• Solid understanding of fault models (stuck-at, transition, path delay, bridging) and of the difference between fault coverage and test coverage.
• Experience with scan compression (for example DFTMAX or EDT) and at-speed testing with OCC.
• Working knowledge of Verilog/SystemVerilog, synthesis flows and STA basics.
• Scripting in Tcl, plus Python or Perl, to automate flows.
• Experience with gate-level simulators such as VCS, Xcelium or Questa.

Preferred qualifications

• Experience with Siemens Tessent (TestKompress, MBIST) or Cadence Modus.
• MBIST and memory repair, LBIST, and hierarchical or core-based DFT.
• Silicon debug and yield learning with volume diagnosis tools.
• Low-power DFT, meaning test with multiple power domains and UPF awareness.
• Advanced process nodes (7nm and below) and cell-aware or small-delay-defect ATPG.

Soft skills

• Strong analytical and debugging skills, and comfort working through complex tool reports.
• Clear communication across design, verification, physical design and test teams.
• Ability to own DFT deliverables on a tapeout schedule.