What are the responsibilities and job description for the Sr. Analog Layout Engineer position at Monolithic Power Systems, Inc.?
Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures. At MPS, we cultivate creativity, are passionate about sustainability, and are committed to providing leading-edge products and innovation to our customers. Our portfolio of technology helps power our world ---come join our team and see how YOU can make a difference.
Job Description
Job Summary
We’re looking for a passionate Analog Layout Engineer who is responsible for physical design of analog and mixed-signal ICs in leading edge sub-micron BiCMOS /DMOS technologies. Products may include switching regulators, hot-swap eFuse, haft-bridge driver and power management ICs for fast growing markets such as networking, server, telecom, notebook/server.
Key Responsibilities
Pay is based on market location and may vary based on factors including experience, skills, education and other job-related reasons. The base salary range for this position in California is $80,000 - $120,000.
Monolithic Power Systems, Inc. (MPS) is an Equal Opportunity Employer and embraces diversity in our employee population. It is the policy of MPS to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, protected veteran status or special disabled veteran, marital status, pregnancy, genetic information, or any other legally protected status.
Job Description
Job Summary
We’re looking for a passionate Analog Layout Engineer who is responsible for physical design of analog and mixed-signal ICs in leading edge sub-micron BiCMOS /DMOS technologies. Products may include switching regulators, hot-swap eFuse, haft-bridge driver and power management ICs for fast growing markets such as networking, server, telecom, notebook/server.
Key Responsibilities
- Conduct Chip floor planning including device placement, matching and routing.
- Run and interpret physical verification checks including DRC, LVS and ERC verifications.
- Develop project schedule and execution plan to meet project milestone deadlines.
- Debug complex verification issues, support off-site design and layout teams.
- Able to work with overseas teams, able to lead a team to deliver high quality layout that meets design requirements.
- Understanding of hierarchical planning and integration, chip design from block-level to top-level.
- Understanding of design rules, device matching, signal shielding, isolation techniques etc.
- Understanding of semiconductor devices as well as CMOS and BiCMOS processes
- Bachelor's degree in engineering OR Certificate Program in Integrated Circuit Layout.
- 7 years of experience designing full-custom Analog & Mixed Signal layouts in CMOS and BiCMOS technology.
- Experience with Cadence Assura, Cadence Virtuoso XL(VXL).
- Be able to complete a project from block-level to top-level to tape-out.
- Data management tools in a Unix environment.
- Effective communication & written skills are the must.
- San Jose, CA
Pay is based on market location and may vary based on factors including experience, skills, education and other job-related reasons. The base salary range for this position in California is $80,000 - $120,000.
Monolithic Power Systems, Inc. (MPS) is an Equal Opportunity Employer and embraces diversity in our employee population. It is the policy of MPS to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, protected veteran status or special disabled veteran, marital status, pregnancy, genetic information, or any other legally protected status.
Salary : $80,000 - $120,000