What are the responsibilities and job description for the Design Verification Engineer position at Mogi I/O : OTT/Podcast/Short Video Apps for you?
Location: Austin, Texas, USA (On-site, 5 days/week – Mandatory)
Work Type: Full-Time, Permanent
Experience Required: 5 – 10 Years
Compensation: USD 160,000 – 180,000 (Annual) Equity
Eligibility: Will sponsor H1-B
Interview Process: 3 rounds, completed within 2 weeks
Job Overview
A well-funded Series-D semiconductor startup (stealth-mode exited, $180M funding) is seeking a Senior Verification Engineer to help build and verify next-generation high-speed optical communication systems (800G, 1.6T and beyond). The role involves comprehensive RTL verification, testbench development, functional coverage, and collaboration with design teams to ensure silicon-ready quality.
You will work on cutting-edge programmable coherent DSP technologies that power cloud, hyperscale, and AI infrastructure.
Key Responsibilities
Work Type: Full-Time, Permanent
Experience Required: 5 – 10 Years
Compensation: USD 160,000 – 180,000 (Annual) Equity
Eligibility: Will sponsor H1-B
Interview Process: 3 rounds, completed within 2 weeks
Job Overview
A well-funded Series-D semiconductor startup (stealth-mode exited, $180M funding) is seeking a Senior Verification Engineer to help build and verify next-generation high-speed optical communication systems (800G, 1.6T and beyond). The role involves comprehensive RTL verification, testbench development, functional coverage, and collaboration with design teams to ensure silicon-ready quality.
You will work on cutting-edge programmable coherent DSP technologies that power cloud, hyperscale, and AI infrastructure.
Key Responsibilities
- Plan and execute verification of complex digital design blocks as per specifications.
- Build advanced verification environments using SystemVerilog and UVM.
- Identify, write, and track functional and coverage metrics including corner-case scenarios.
- Debug digital functionality closely with RTL design teams and system architects.
- Perform full coverage collection and ensure coverage closure across all verification stages.
- Participate in block and system-level verification cycles.
- Contribute to architectural discussions related to next-generation DSP systems and optical communication.
- Minimum 5 years of total experience, including 3 years in verification.
- Strong knowledge of VLSI verification flow, concepts, and methodologies.
- Hands-on experience building environments using SystemVerilog UVM / eRM / OVM.
- Completed at least one full block or system-level verification cycle.
- Experience with data path or data protocols (Ethernet preferred).
- Strong debugging, problem-solving, and communication skills.
- Ability to work on-site in Austin (no remote option).
- H1-B sponsorship available.
- Experience writing complex functional coverage for corner-cases.
- Prior involvement in digital block planning and verification strategy creation.
- Knowledge of mixed-signal or analog/digital co-verification.
- Ability to write structured test plans and present results to multi-functional teams.
- Experience in high-speed communication, DSP, optical, or networking chipsets.
Salary : $160,000 - $180,000