What are the responsibilities and job description for the Design Verification Engineer position at Mirafra Technologies?
Title Design Verification Engineer
Location San Jose CA
Full Time role
Key responsibilities
- Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon).
- Work closely with software and application developers on identifying performance bottlenecks and tuning the software.
- Develop test plans and test infrastructure/tools for performance tuning, correlation, and verification.
- Improve and maintain the architectural performance models.
- Develop tests in SystemVerilog, Python, or vectors to debug and correlate the RTL and performance model.
- Develop SystemVerilog or Python-based checkers for verifying the performance features.
- Develop coverage monitors and analyze coverage to ensure all performance features are covered.
- Debug performance issues and conduct performance tuning on silicon.
- Drive end-to-end performance tuning, ensuring optimal hardware utilization, software efficiency, and architectural alignment across the ASIC design lifecycle.
You may be a good fit if you have
- Strong understanding of digital design, RTL, and ASIC design flows.
- Hands-on experience with performance verification, simulation, and modeling.
- Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog.
- Skilled in writing Python scripts for automation, data analysis, and performance modeling.
- Experience building and maintaining performance models for chip subsystems.
- Understanding of memory hierarchies, pipelines, interconnects, and compute accelerators.
- Familiarity with performance bottleneck analysis, compiler optimizations, and workload tuning
- Some exposure to kernel level performance metrics and profiling tools.