Senior Principal Analog Design Engineer

Micron’s DRAM Design Engineering Group (DDEG) is where bold ideas become real technology. We push the limits of memory and storage innovation, and we thrive in a collaborative environment where engineers learn, build, and solve challenges together. We are driven by curiosity, creativity, and the pursuit of better solutions every day!

We are seeking a Principal or Member of Technical Staff (MTS) (Sr. Principal) in Analog Design in Boise, Idaho to join our DRAM IP Design team. As a Principal/MTS, you will help shape the next generation of Micron's memory products, while working closely with global design, verification, and product teams to bring innovative circuit designs from concept to silicon. Your work will directly influence product performance, quality, and reliability—and contribute to advancements that define the semiconductor industry.

Responsibilities:

• Design, optimize, and verify block‑level analog and mixed-signal circuits for DRAM projects.
• Work with the internal data science team and EDA vendors to leverage and improve AI-assisted design flow and circuits optimization.
• Propose, evaluate and implement new or improved circuit topology to further enhance PPAC of the circuit block.
• Improve design verification scope and coverage to increase circuit robustness to enhance mass production yield.
• Partner with global design groups and provide layout guidance through post‑layout simulation.
• Compare silicon performance with simulation results and support correlation activities.
• Mentor junior circuit designers and operate with minimal supervision on defining solutions and methods independently.

Minimum Qualifications:

• Bachelor’s degree in Electrical Engineering with 12 years of semiconductor design experience.
• Solid analog circuit design fundamentals and experience designing fundamental analog blocks such as regulators, charge pumps, oscillators, current references, bandgaps, or comparators.
• Proficiency with SPICE and Verilog modeling and simulation.
• Ability to supervise physical layout work of analog circuits.
• Experience collaborating with technical and non‑technical teams.

Preferred Qualifications:

• MSEE 12 years or BSEE 15 years of mixed‑signal or analog IC design experience in a fast-paced environment.
• Prior demonstrated experience in DRAM circuits design and 5 years of circuit debugging experience with cross‑functional teams.
• Good understanding of device physics and CMOS process technologies.
• Demonstrated ability in mentoring and coaching junior engineers.

Total Compensation Package (Base Stocks Bonus) $300K to $400K DOE