Senior Engineer II-Verification

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

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Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

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Job Description

Microchip is seeking a highly skilled and experienced Senior Verification Engineer to join the Advanced Engineering Services team at our Fab 4 facility in Gresham, Oregon. The successful candidate will be responsible for leading the development and implementation of comprehensive verification plans to ensure optimal functionality of our manufactured devices.

Essential Functions

• Develop verification test plans from design specifications.
• Build verification environments for chip/module level designs using SystemVerilog with UVM.
• Develop test cases using transaction based checkers to execute verification test plans.
• Manage and Launch regressions using Cadence tools such as Verisium Manager and Xcelium Simulator.
• Interpret simulation results using tools such as Simvision to root cause discrepancies between expected and simulated results in collaboration with the design team.
• Generate and analyze code and functional coverage to ensure adherence to the test plan.
• Promote and apply advanced verification techniques including constrained random generation, functional coverage, assertions, and formal verification.
• Work with CAD team to resolve tool related issues and provide test cases, as required.
  
  

Requirements/Qualifications

• MS degree in EE/CE with 5 years of industry experience or B.S degree in EE/CE with 7 years of industry experience preferably in ASIC or FPGA environments.
• Proficient in HDL languages SystemVerilog, Verilog and VHDL.
• Apply UVM based verification using coverage driven verification techniques.
• Hands-on experience with assertion-based verification (ABV), including writing and debugging SystemVerilog Assertions (SVA).
• Experience with formal verification and assertion analysis tools such as Fishtail, JasperGold, or similar.
• Familiarity with the Linux compute environment.
• Excellent analytical and problem-solving skills.
• Ability to clearly express complex design concepts and simulation results, both verbally and in written form.
• Proactive and able to work independently or as part of a team.
• Experience with using scripting languages (Python, Perl, Tcl) for automation.
  
  

Preferred Qualifications

• Object Oriented programming
• Understanding of ASIC designs and verification methodologies
• Domain Expertise : AHB, AXI, PCIe.
• Experience with additional simulation tools (e.g., VCS, ModelSim)
  
  

Travel Time

0% - 25%

Physical Attributes

Bending at Waist, Feeling, Handling, Kneeling, Lifting, Pulling, Pushing, Reaching, Seeing, Stooping, Talking, Works Alone, Works Around Others

Physical Requirements

Lifting

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.

To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.