Embedded Software Engineer (Real Time Edge Compute)

Company Overview 

Metrea delivers effects-as-a-service to national security partners across five domains and more than a dozen mission areas—including airborne ISR, electronic warfare, secure communications, aerial refueling, special mission aviation, aerial firefighting, and advanced simulation. 

Wherever we operate, we build vertically integrated full stacks of capability—designing, building, and operating turnkey solutions that let customers scale capacity while benefiting from continuous cycles of innovation. With operators and engineers under one roof, we close the gap between lab and field—what we call connecting design with effect. 

Metrea’s solutions are built for elegance: effective, efficient, and evolving. This approach enables our partners to do more with less and achieve outsized, asymmetric advantage against rapidly evolving threats. 

Headquartered in Washington, DC, Metrea has facilities across the United States, the United Kingdom, Europe, and beyond.

 
Group Overview:

Electromagnetic and Cyber Group (EM&C) is responsible for developing flexible and survivable advanced electronic warfare and secure communications equipment while providing the industry’s leading signals intelligence, electronic warfare, and cyber experts. Metrea specializes in signal classification, direction finding, advanced geolocation techniques, and waveform development including waveforms for MANET and LPI/LPD applications. Metrea also develops special purpose radios for government customers and licenses DF and geolocation solutions to multiple OEMs.

Position Summary 

The Embedded Software Engineer (Engineer II) develops and integrates embedded software and firmware components that mature RADLAB radar R&D algorithms into a robust, testable, real-time processing system on high performance edge CPU/GPU/FPGA platforms. This role focuses on implementing high-rate sensor ingest pipelines, building record/replay and validation infrastructure, integrating SDR and compute platforms, and optimizing performance to meet defined latency, throughput, and determinism targets under guidance from senior technical leadership.

Role and Responsibilities 

• Platformbring-up and integration:Get new SDR andcomputehardwarerunning:drivers, configuration, streaming, clock discipline, and sustained-load stability testing.

• High-throughput data pipelines:Build andmaintainthe path from sensor ingest through embeddedcomputeand into storage, including buffering, backpressure, record/replay, and integrity verification.
• Real-time performance:Design for determinism: timing budgets, scheduling, concurrency, lock contention avoidance, and meeting latency/jitter targets under load.
• Algorithm fidelity:Ensure the embedded implementation matches the engineering model. Define equivalence tolerances,validateagainst golden vectors, andwork with the team torecognize when something is wrong at the algorithm level, not just the software level.
• Performance optimization:Profile and tuneCPU affinity, NUMA placement, cache efficiency, zero-copy dataflow,GPUDirectRDMA/Storage, GPU kernel throughput, and storage subsystem configuration for sustained high-rate operation.
• Testing and CI/CD:Build repeatable test rigs, automate regression testing, and hook hardware-coupled validation into the CI pipeline.
• Communication:Flag practical constraints early (throughput, latency, memory, real-time feasibility) and work withthe teamon mitigations before they become blockers.

Required Skills and Experience 

• BS/MSin Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience;at least3–6 yearsof focus inembeddedand/or high-performancereal-timesystems.Specifically:
  

• StrongC/C systems programming:concurrency, memory management, profiling,andcleanmoderninterfaces.
• Experience with platform bring-up:drivers, device configuration, high-rate streaming, cross-layer debugging.
• Low-latency / high-throughput streaming systems:buffering, loss detection, failure modes, graceful degradation.

• Real-time engineering experience:timing analysis, deterministic scheduling, bounded-latency design.
• Debugging with professional tools:GDB/JTAG, logic analyzers, perf/ftrace, packet traces.
  
• Automated testing:golden vector validation, structured pass/fail gates, CI integration.
  
• Clear written communicationfor validation reports and integration risk tracking.

Bonus Qualifications 

• Ettus/UHD SDR ecosystemexperience, multi-core HPC systems, precise time/clock synchronization.
  
• GPU-accelerated signal processing:asyncpipelines,GPUDirectRDMA/Storage, kernel throughput optimization.
  
• FPGA HLS experience (C -based; RTLnotrequired).
  
• Linux performance engineering (affinity, scheduling, network/I/O tuning) or RTOS experience.
  
• Enoughalgorithm familiarityto recognize when an implementation isfundamentally inefficient.

Additional Eligibility Qualifications 

• U.S. Citizenship
  
• Ability to obtain andmaintaina TSsecurity clearance.
  
• Strong communicationand collaboration skills for cross-functional team environments.
  
• Commitment to reproducibility,documentation, andengineering and mathematical rigor.