Design for Test Engineering Intern - Bachelor's Degree

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Custom and Compute Business Unit in Marvell is a world leader in advanced node semiconductor engineering. The team is developing high core-count AI compute platforms, 5G and 6G acceleration silicon, and custom ASIC designs for industry leading customers. Designs are large, complex, and challenge current design and manufacturing limits. Multi-die, 2.5D and 3D designs guarantee that Marvell remains at the forefront, delivering the highest and most integrated solutions that customers require.

What You Can Expect

This engineer will work with a high-performing DFT/DV team within a DFT organization. Work assignment will be in two areas. The first area will be design verification, at block and full-chip, of DFT IP inserted at RTL level. This verification effort is UVM based. This role also presents opportunities in ATE pattern development. The second area will be using Siemens EDA tool to insert DFT test logic and to verify this logic after insertion.

In This Role You Will Work On

• UVM test case development when new DFT RTL is added into a design. You will have the opportunity to gain experience in DFT architecture given the requirement that underlying logic be thoroughly tested in RTL form.
• Opportunities for script development where technical details of the underlying DFT architecture are abstracted into control files which then allow developing design verification flows that can span a generation of designs.
• Opportunity to work with JTAG, 1687, end evolving chiplet to chiplet test busses.
• Use of 1687 ICL/PDL to automate the creation of functional test patterns deployed on ATE. Like structured (ATPG/memory BIST) patterns, functional patterns leverage automation. A functional test pattern may load via JTAG or through a proprietary bus. In the end this functional pattern may interact directly with registers or load code into a processor resident in the DUT which then runs the test case. The complexity of these patterns requires that automated approaches be deployed to create them and to allow quicker regeneration.
• Debug of high speed IOs to include DDR and SERDES, collaborating with designers, internal and third-party IP developers, to understand test requirements, help architect test access, verify the proper integration in the netlist, develop patterns, and support ATE bring-up and debug.
• Use of Siemens EDA tools to insert scan and memory BIST, and the verification of these inserted test elements.
  
  

What We're Looking For

• Working towards a Bachelor’s degree in Computer Science, Electrical Engineering or related fields
• VLSI/SCAN/ATPG and UVM/Verification coursework preferred
• Desire to work with scan/ATPG, memory BIST, using Siemens tools
• Desire to work with System Verilog, UVM, Verification Test Plans, Coverage Driven Verification, Code Coverage, verification environments, test case simulation and debug.
  
  

Expected Base Pay Range (USD)

28 - 55, $ per hour.

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation And Benefit Elements

For Internship roles, we are proud to offer the following benefits package during the internship - medical, dental and vision coverage, perks and discount programs, wellness & mental health support including coaching and therapy, paid holidays, paid volunteer days and paid sick time. Additional compensation may be available for intern PhD candidates.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.