What are the responsibilities and job description for the Modelling Lead (SystemC / Virtual-Platform Architect) position at Lumilens?
About Lumilens
At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient.
We’re a well-funded startup backed by Mayfield and led by veterans who’ve built and scaled some of the most transformative technologies in the industry.
This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. The market is moving fast, and we’re moving faster. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.
If you're looking for mission, momentum, and the chance to make an outsized impact, jump on the rocket ship. We’re just getting started.
About the role. You will build the executable model of the chip before silicon exists. Your architecture models will settle the decisions that are expensive to change late, including datapath latency, throughput, buffer sizing, and control-loop tuning. Your reference models will become the golden checkers the verification team scores against, and the platform will run real firmware months ahead of RTL. This is a founding, critical-path role: the virtual platform is what unblocks the firmware and architecture work in parallel with design.
What You'll Own
At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient.
We’re a well-funded startup backed by Mayfield and led by veterans who’ve built and scaled some of the most transformative technologies in the industry.
This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. The market is moving fast, and we’re moving faster. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.
If you're looking for mission, momentum, and the chance to make an outsized impact, jump on the rocket ship. We’re just getting started.
About the role. You will build the executable model of the chip before silicon exists. Your architecture models will settle the decisions that are expensive to change late, including datapath latency, throughput, buffer sizing, and control-loop tuning. Your reference models will become the golden checkers the verification team scores against, and the platform will run real firmware months ahead of RTL. This is a founding, critical-path role: the virtual platform is what unblocks the firmware and architecture work in parallel with design.
What You'll Own
- A SystemC/TLM-2.0 virtual platform — MCU (ISS-backed) peripherals memory map a UCIe transactor host stub — that firmware runs on pre-RTL.
- Architecture/performance models: architectural trade studies, end-to-end datapath throughput and latency, FIFO/buffer sizing, design-space/configuration exploration.
- Golden reference models handed to DV as scoreboards.
- Behavioral models of the analog and control circuits.
- Partner with the FE architect and firmware lead to keep model, RTL, and firmware views coherent.
- 8 years in architecture/performance modelling or virtual-platform development for complex SoCs.
- Strong SystemC and TLM-2.0; solid modern C .
- Built or led a virtual platform / ESL model that real firmware ran on for pre-silicon bring-up.
- Integrating a third-party ISS (e.g., Arm or RISC-V) into a SystemC/TLM platform; modelling buses, memory maps, and peripherals.
- Architecture/performance modelling judgment — knowing what to abstract versus model faithfully.
- Comfortable spanning hardware micro-architecture and embedded software.
- Familiarity with High-speed serial links and die-to-die / chiplet interconnects, and link-layer concepts such as FEC and equalization (e.g. PCIe, UALink, Ethernet or memory-semantic interconnects like CXL).
- Experience feeding golden models into a UVM/DV verification flow.
- Modelling for mixed-signal or optical/SerDes systems, including control-loop / plant modelling.
- High-throughput datapath modelling.
- Competitive salary commensurate with experience
- Comprehensive benefits package including health, dental, and vision
- Professional development opportunities and certification support
- Access to cutting-edge technology and cloud platforms
- Collaborative work environment with cross-functional teams