Principal Analog IC Design Engineer

Responsibilities

Kforce's client, a rapidly growing and well-established semiconductor company in Camarillo, CA, is seeking a Principal Analog IC Design Engineer to join their team. We are working directly with the hiring manager on this exclusive search. The company offers a highly competitive compensation package, including base salary, annual bonus, and equity. This position is 100% onsite. Summary: We are looking for an experienced Senior or Principal Analog IC Design Engineer to lead the development of cutting-edge transimpedance amplifiers (TIAs) operating in the multi-tens of GHz range. These optical interface chips are tightly integrated with our high-performance equalizers and are recognized as best-in-class for coherent long-haul, metro systems, and PAM4 data center applications. Responsibilities:

• Leading active circuit design and providing technical leadership
• Designing advanced TIAs using SiGe BiCMOS and FinFET CMOS technologies, pushing performance beyond industry benchmarks
• Developing millimeter-wave transmission line structures to achieve superior performance
• Creating high-performance broadband analog circuits for optical front-end receivers
• Designing supporting analog blocks such as linear regulators, AGC loops, current/voltage sensors, bandgaps, etc.
• Defining microarchitecture for major circuit blocks and guiding a team of designers through implementation
• Collaborating cross-functionally to support post-silicon validation, qualification, mass production, and customer engagement
  
  

Requirements

• Bachelor's degree in Electrical Engineering with 8-12 years of relevant industry experience, or Master's/PhD with 5 years of experience in high-performance RF/Analog Receiver or TIA design or Drivers
• Proven track record in chip tape-out and lab evaluation of high-performance receivers
• Proficiency with EDA CAD tools and hands-on experience in IC performance measurement and debugging
• Strong foundation in transistor-level design, device physics, and control/feedback loop stability analysis
  
  

Preferred

• Experience with multiple technologies, especially SiGe BiCMOS and FinFET CMOS
• Leadership experience mentoring junior designers and serving as chip lead
• Successful track record of taking chips to mass production
• Ability to translate chip-level specifications into architectural designs
• Experience with analog custom layout
  
  

Plus

• AGC loop design
• High-precision analog circuits (e.g., linear regulators, current sensors, bandgaps, drivers, DAC/ADC)
• Continuous-time linear equalizers
  
  

The pay range is the lowest to highest compensation we reasonably in good faith believe we would pay at posting for this role. We may ultimately pay more or less than this range. Employee pay is based on factors like relevant education, qualifications, certifications, experience, skills, seniority, location, performance, union contract and business needs. This range may be modified in the future.

We offer comprehensive benefits including medical/dental/vision insurance, HSA, FSA, 401(k), and life, disability & ADD insurance to eligible employees. Salaried personnel receive paid time off. Hourly employees are not eligible for paid time off unless required by law. Hourly employees on a Service Contract Act project are eligible for paid sick leave.

Note: Pay is not considered compensation until it is earned, vested and determinable. The amount and availability of any compensation remains in Kforce's sole discretion unless and until paid and may be modified in its discretion consistent with the law.

This job is not eligible for bonuses, incentives or commissions.

Kforce is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.

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