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Job Title:Thermal Engineer Job ID:26-02435 Location: CA, SAN JOSE, 95124 Duration: 12 months on W2 contract
JOB DUTIES:
Defining and implementing test plans, developing System Verilog /UVM based unit level test benches, including stimulus, checkers, monitors and assertions, analyzing and debugging regression fails, and developing and analyzing functional coverage on North Bridge / Data Fabric Design.
Key skills are software (System Verilog, C/C , object oriented programming, scripting (e.g. Perl), x86 assembly), Verilog simulation and modeling, knowledge of computer and peripheral architectures.
EXPERIENCE AND EDUCATION:
Bachelors and 0-2 years experience, or Masters and 2 years experience;
Requires demonstrated technical expertise in functional verification of microprocessor designs;
Experience with Verilog, System Verilog, UVM, programming in Perl & C/C , logic simulation is a requirement;
Requires very strong understanding of computer architecture;
Experience of assertion based design strategies, code coverage, functional coverage etc will be an asset;
Requires good communication and technical leadership skills
Compensation:
The hourly rate for this position is Up To $60 per hour.
Factors which may affect starting pay within this range may include [geography/market, skills, education, experience and other qualifications of the successful candidate].
Job Title:Thermal Engineer Job ID:26-02435 Location: CA, SAN JOSE, 95124 Duration: 12 months on W2 contract
JOB DUTIES:
Defining and implementing test plans, developing System Verilog /UVM based unit level test benches, including stimulus, checkers, monitors and assertions, analyzing and debugging regression fails, and developing and analyzing functional coverage on North Bridge / Data Fabric Design.
Key skills are software (System Verilog, C/C , object oriented programming, scripting (e.g. Perl), x86 assembly), Verilog simulation and modeling, knowledge of computer and peripheral architectures.
EXPERIENCE AND EDUCATION:
Bachelors and 0-2 years experience, or Masters and 2 years experience;
Requires demonstrated technical expertise in functional verification of microprocessor designs;
Experience with Verilog, System Verilog, UVM, programming in Perl & C/C , logic simulation is a requirement;
Requires very strong understanding of computer architecture;
Experience of assertion based design strategies, code coverage, functional coverage etc will be an asset;
Requires good communication and technical leadership skills
Compensation:
The hourly rate for this position is Up To $60 per hour.
Factors which may affect starting pay within this range may include [geography/market, skills, education, experience and other qualifications of the successful candidate].
Salary : $60