What are the responsibilities and job description for the Senior FPGA Verification Engineer position at Jobs via Dice?
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3 years of FPGA verification experience
Strong SystemVerilog programming skills
Hands-on experience with UVM (Universal Verification Methodology)
Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS)
Experience with code and functional coverage analysis
Proficient in debugging and problem-solving
Scripting experience in Python or Perl
Knowledge of Verilog and/or VHDL
3 years of FPGA verification experience
Strong SystemVerilog programming skills
Hands-on experience with UVM (Universal Verification Methodology)
Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS)
Experience with code and functional coverage analysis
Proficient in debugging and problem-solving
Scripting experience in Python or Perl
Knowledge of Verilog and/or VHDL
