Physical Design Engineer in California

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Hi,

Physical Design Engineer

Santa Clara, CA - 5 days onsite no remote

Longterm

Full-Time / Contract

Open to All Visa Types

Experience: 5 15 Years

Job Description

We are seeking an experienced Physical Design Engineer to join a high-performance semiconductor team working on cutting-edge SoC and ASIC designs. The ideal candidate will have strong hands-on expertise in RTL-to-GDSII implementation and signoff flows for advanced technology nodes.

Key Responsibilities

• Execute full-chip and block-level physical design implementation
• Perform floorplanning, placement, CTS, routing, and physical verification
• Handle timing closure, congestion analysis, and power optimization
• Work closely with RTL, DFT, STA, and PD teams for design convergence
• Analyze and resolve setup/hold violations and signal integrity issues
• Support low-power implementation techniques and ECO flows
• Drive design closure for advanced nodes including 7nm/5nm/3nm technologies
• Collaborate with backend and frontend teams for tapeout readiness
  
  

Required Skills

• Strong experience with Physical Design flow from Netlist to GDSII
• Expertise in floorplanning, placement, CTS, routing, and timing closure
• Hands-on experience with tools such as Cadence Innovus, ICC2, PrimeTime, Tempus, Calibre
• Knowledge of STA, IR drop, EM analysis, DRC/LVS verification
• Experience with advanced technology nodes preferred
• Strong scripting skills in Tcl, Perl, or Python
• Excellent debugging and problem-solving skills
  
  

Preferred Qualifications

• Experience with low-power design methodologies
• Knowledge of UPF/CPF flows
• Prior tapeout experience on complex SoCs or high-speed designs
• Strong communication and collaboration skills