What are the responsibilities and job description for the GPU Design Implementation, Static Timing Analysis Engineer position at Jobs via Dice?
Job Description
Title: Senior Staff GPU Design Implementation, Static Timing Analysis Engineer
Location: Austin, TX or San Jose, CA. onsite strongly preferred
Need: "STA engineer with strong PrimeTime experience who has owned timing closure at ?5nm."
Position Summary We are seeking a Senior Staff Static Timing Analysis (STA) Engineer for our client to help shape timing integrity and signoff readiness for their next-generation GPU IPs.
This individual contributor role will join the GPU Physical Design team to collaborate with RTL, physical design, SoC integration, and EDA partners to develop and implement timing analysis and convergent strategies for complex GPU designs. The ideal candidate brings strong hands-on STA expertise, deep understanding of ASIC design flows, and a collaborative mindset to apply sound methodology and deliver high-quality timing closure across functional and test modes.
Title: Senior Staff GPU Design Implementation, Static Timing Analysis Engineer
Location: Austin, TX or San Jose, CA. onsite strongly preferred
Need: "STA engineer with strong PrimeTime experience who has owned timing closure at ?5nm."
Position Summary We are seeking a Senior Staff Static Timing Analysis (STA) Engineer for our client to help shape timing integrity and signoff readiness for their next-generation GPU IPs.
This individual contributor role will join the GPU Physical Design team to collaborate with RTL, physical design, SoC integration, and EDA partners to develop and implement timing analysis and convergent strategies for complex GPU designs. The ideal candidate brings strong hands-on STA expertise, deep understanding of ASIC design flows, and a collaborative mindset to apply sound methodology and deliver high-quality timing closure across functional and test modes.
- Help shape hands-on static timing analysis strategy at top level, developing, debugging, and maintaining timing constraints, clock definitions, and timing environments for complex, multi-clock GPU IPs across functional and test scenarios.
- Drive timing closure and signoff readiness by analyzing timing paths, understanding different clocking and implementation styles, managing latency and skew tradeoffs, and applying timing budgeting, derating, and multi-voltage methodologies across advanced process nodes.
- Advance cross-functional collaboration with RTL, physical design, and SoC teams to identify, debug, and resolve timing issues impacting block-level and full-chip closure, ensuring alignment between logical intent and physical implementation.
- Influence STA methodologies and sign-off flows, leveraging industry-standard tools and exploring best practices-including POCV, multi-corner analysis, and low-power constraints-to improve timing quality, convergence, and predictability.
- Advance best practices by maintaining technical documentation and staying ahead of emerging GPU technologies.
- 11 years of experience with a Bachelor's Degree in Computer Science/Engineering, or 9 years of experience with a Master's Degree, or 7 years of experience with a Ph.D.
- 7 years of hands-on experience with ASIC design flows and electrical engineering fundamentals.
- Strong experience with POCV, derating methodologies, and timing analysis.
- Strong hands-on experience with industry-standard STA tools (e.g. PrimeTime, Tempus), clock tree synthesis (CTS), multi-voltage and multi-clock designs.
- Strong knowledge of formal equivalency checks, low-power checks, timing constraints, UPF.
- Strong scripting /programming skills in Tcl, Perl, Shell, and/or Python.
- Strong analytical skills, attention to detail, and problem-solving skills using data-driven approach.
- Experience with leading technical initiatives, driving process and methodology innovation, and mentoring engineers
- Excellent collaboration and communication skills, with the ability to navigate ambiguity and influence stakeholders in a fast-paced, global team environment.
- Familiarity with advanced FinFET process nodes (5nm or smaller).
- Hands-on experience with synthesis, block and/or full chip implementation with the latest industry P&R/STA flows and tools.
- Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure.