FPGA Engineer at Waukesha, WI

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Position: FPGA Engineer VHDL

Experience: -5 Years

Location: -Waukesha, WI(Onsite)

Responsibilities: -

• Architecture & Development (VHDL Focused) Own FPGA RTL design using VHDL as the primary HDL. Develop reusable IP blocks including state machines, controllers, DSP modules, and memory interfaces.
• Implement deterministic, low-latency data paths for diagnostic imaging and acquisition systems.
• Translate system requirements into FPGA architecture with complete traceability.
• High-Speed I/O & Data Acquisition (MedTech) Implement and validate interfaces for precision ADC/DAC front ends: JESD204B/C, LVDS, MIPI, SPI, I C, UART.
• Build high-throughput acquisition and buffering pipelines using DDR4/DDR5 and AXI.
• Ensure deterministic timing, synchronization, and clocking across modalities (Ultrasound/ CT/MRI/sensing subsystems).
• Verification, Timing Closure & Tool flow: Develop self-checking VHDL testbenches for block and system level verification.
• Use ModelSim/QuestaSim, Vivado Simulator, or Riviera PRO for simulation. Perform synthesis, P&R, timing analysis, and closure using Xilinx Vivado (preferred) or Intel Quartus.
• Execute linting, CDC/RDC checks, and optimize power and resource utilization.
• Debug via ILA/SignalTap, oscilloscopes, logic and protocol analyzers. Compliance, Documentation & Quality Support design controls and documentation for FDA, EU MDR, and global regulatory needs.
• Contribute to requirements traceability (Jama/DOORS), risk management (ISO 14971), and verification per IEC 62304 for programmable logic.
• Address safety (IEC 60601 1), EMC (IEC 60601 1 2), cybersecurity, FMEA, hazard analysis, and IP/SOUP assessments.
  
  

Educational Qualifications: -

Bachelor's or Master's in Electronics, Electrical, Computer Engineering, or related field.

Mandatory Skills

• 4 10 years of hands-on FPGA design experience with VHDL as the primary HDL.
• Strong experience with: Synchronous digital design fundamentals, Clocking, CDC, reset-domain considerations, Timing analysis and closure, FPGA development using Xilinx/AMD.
• Proven ability to develop complex state machines, DSP blocks, and interface logic in VHDL.
• Familiarity with lab bring-up and FPGA system debugging.
  
  

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