What are the responsibilities and job description for the DDR Engineer position at Jobs via Dice?
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Key skills: Zebu, FPGA , DDR (All generations) , ARM, DDR PHY, logic analyzers, oscilloscopes, and simulation waveforms
Key skills: Zebu, FPGA , DDR (All generations) , ARM, DDR PHY, logic analyzers, oscilloscopes, and simulation waveforms
- Ensuring DDR PHY and controller designs adhere strictly to JEDEC standards (DDR4/DDR5/LPDDR5/LPDDR6)
- Using simulators (e.g., VCS) and emulators (e.g., ZeBu, Cadence Palladium) to debug design failures and root cause issues before tape-out.
- Validating power-sensitive LPDDR5 states, including self-refresh and deep power-down modes.
- Running simulations to verify timing margins, memory throughput, and latency, often collaborating on Python scripting for automation.
- Ensuring proper integration between the DDR controller, PHY, and SoC firmware
- Develop and execute test plans in C to validate the Features. In depth knowledge of one or more peripheral protocols and specifications Bare metal/Linux driver development, Firmware development.
- Understanding Pre-Silicon Validation for DDR4/LPDDR4/LPDDR5
- Pre-silicon validation means verifying design and firmware before the silicon chip is fabricated. It includes simulations, emulation, and formal verification to catch bugs early. For DDR memory interfaces (DDR4, LPDDR4, LPDDR5), pre-silicon validation focuses on:
- Protocol compliance (timing, command sequences, training sequences)
- Signal integrity modeling and timing margins
- Firmware interactions (training firmware, calibration sequences)
- Power management features (especially for LPDDR5 with deeper power states)
- Using hardware description languages (HDL) and simulators (like Synopsys VCS, Cadence Incisive) for DDR PHY and controller
- Proficient in C for low-level firmware
- Ensuring DDR commands follow JEDEC standards (DDR4/LPDDR4/LPDDR5 specs)
- Debugging skills using logic analyzers, oscilloscopes, and simulation waveforms