What are the responsibilities and job description for the Principal Physical Design Engineer (STA) position at Jobright.ai?
Jobright is an AI-powered career platform that helps job seekers discover the top opportunities in the US. We are NOT a staffing agency. Jobright does not hire directly for these positions. We connect you with verified openings from employers you can trust.
Job Summary:
Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. As a Principal Physical Design Engineer (STA), you will be responsible for driving the planning, coordination, and execution of the design of connectivity ASICs for leading cloud service providers and OEMs, working closely with various engineering teams.
Responsibilities:
• Drive the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs.
• Work closely with designers, verification engineering, and engineering operations.
Qualifications:
Required:
• Strong academic and technical background in electrical engineering. A bachelor's degree in EE / Computer Science is required, and a master's degree is preferred.
• ≥12 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and a can-do attitude. Think and act fast with the customer in mind!
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, and timing closure at the block and full-chip level.
• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of System Verilog/Verilog.
• Experience with DFT tools and techniques.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in tcl, python, or Perl.
Preferred:
• Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
• Familiarity with DFT test coverage and debug.
• Familiarity with ECO methodologies and tools.
Company:
Astera Labs is a semiconductor company that provides connectivity solutions for intelligent systems. Founded in 2017, the company is headquartered in San Jose, California, USA, with a team of 201-500 employees. The company is currently Public Company. Astera Labs has a track record of offering H1B sponsorships.