What are the responsibilities and job description for the IP Methodology and Automation Engineer position at Intel?
Job Details
Job Description:
The Role And Impact
As a Physical Design Methodology Engineer, you will drive innovation in the development and enhancement of tools, flows, and methods (TFM) that are essential for Intel's physical design implementation across IPs and SoCs. Your work will directly impact the efficiency, quality, and scalability of chip designs, enabling Intel to deliver robust, high-performance, and power-optimized solutions to market. Collaborating with multidisciplinary teams, you will identify gaps, propose transformative changes, and shape the future of physical design methodology, ensuring Intel stays ahead in the ever-evolving semiconductor industry.
Key Responsibilities
Qualifications
Minimum Qualifications:
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location:
US, Texas, Austin
Additional Locations:
Business Group
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00 - 269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Job Description:
The Role And Impact
As a Physical Design Methodology Engineer, you will drive innovation in the development and enhancement of tools, flows, and methods (TFM) that are essential for Intel's physical design implementation across IPs and SoCs. Your work will directly impact the efficiency, quality, and scalability of chip designs, enabling Intel to deliver robust, high-performance, and power-optimized solutions to market. Collaborating with multidisciplinary teams, you will identify gaps, propose transformative changes, and shape the future of physical design methodology, ensuring Intel stays ahead in the ever-evolving semiconductor industry.
Key Responsibilities
- Conceptualize, document, and design TFMs used in physical design implementation for IPs and SoCs.
- Establish regression flows and drive improvements in RTL to GDS flows.
- Develop and implement methodologies to optimize power, performance, area, and timing in physical design constraints.
- Create innovative scripts, checkers, and CAD-based automation to simplify and accelerate design processes.
- Analyze retrospective data on current designs to identify quality and efficiency gaps, driving incremental and transformative improvements.
- Partner with cross-functional teams, including physical design, circuit design, CAD, RTL, tool/flow owners, and third-party vendors, to improve methodologies and ensure alignment.
- Lead initiatives to develop advanced physical design techniques for floor planning, clock tree synthesis, place and route, and multi-power plane (MPP/UPF) designs.
- Support the integration of new tools and methods into existing design workflows, ensuring seamless adoption and scalability.
- Architect, Design, develop, and maintain robust regression and QA automation frameworks specifically for Memory & Mixed signal Hard IP, ensuring comprehensive validation and signoff automation systems with scalability and performance optimization.
- Integrate automation frameworks with existing development pipelines, develop full-stack solutions for data management and reporting, and create APIs/interfaces for seamless tool integration across various systems.
- Implement monitoring and alerting mechanisms for automated test execution, continuously improve testing processes, version control, automation coverage, and ensure framework reliability and performance standards.
- Build comprehensive validation systems that integrate with multiple tools and platforms, focusing on scalability, maintainability, and continuous improvement of QA methodologies for semiconductor IP verification.
Qualifications
Minimum Qualifications:
- Bachelors with 8 years of experience or Master's degree in Electrical Engineering, Computer Engineering, or a related field with 4 years of professional experience; or PhD with 2 years of experience.
- Expertise with EDA tools, physical design flows, and methodologies.
- Experience in TCL and PERL scripting for automation and flow development.
- Experience with SoC integration and RTL to GDS design flows.
- Hands-on experience with design optimization techniques, including synthesis, clock tree synthesis, place and route, and floor planning.
- Experience with the following:
- Multi-power plane designs and integration of UPF methodologies.
- Analyze and improve physical design performance metrics (power, timing, area).
- Leadership & Communication: Demonstrated project management experience handling multiple concurrent projects with excellent cross-team collaboration skills and proven ability to lead technical execution and drive results.
- Programming & Development Skills: Expert-level proficiency in Python, Perl, Tcl, and SKILL with full-stack development experience and proven ability to build and maintain large-scale automation frameworks for complex technical environments.
- CI/CD & Database Experience: Hands-on experience with Jenkins, GitLab CI platforms, SQL/NoSQL databases, and integrating AI/ML technologies into automation frameworks for enhanced testing capabilities.
- Semiconductor Domain Expertise: Deep understanding of semiconductor IP design flow, verification processes, and EDA tools combined with strong analytical and troubleshooting capabilities for complex technical challenges.
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location:
US, Texas, Austin
Additional Locations:
Business Group
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00 - 269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Salary : $141,910 - $269,100