What are the responsibilities and job description for the AI Frameworks Architect position at Intel Corporation?
Job Details
Job Description:
The Intel NPU IP Architecture team is looking for an AI Frameworks Architect to lead VPU architecture performance modeling and analysis activities.
In this position, you will function as a senior technical member in the NPU architecture performance COE (center-of-excellence) team. The primary responsibility of the team includes developing the next generation NPU architecture performance model and conducting performance analysis using models from various benchmarking suites or customer end-to-end use cases.
The role’s responsibilities include but are not limited to:
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications could be obtained through a combination of schoolwork, classes, research, and/or relevant previous job and/or internship experiences.
Minimum Qualifications
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro, US, Oregon, Portland
Business Group
The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $170,500.00 - 315,490.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
Job Description:
The Intel NPU IP Architecture team is looking for an AI Frameworks Architect to lead VPU architecture performance modeling and analysis activities.
In this position, you will function as a senior technical member in the NPU architecture performance COE (center-of-excellence) team. The primary responsibility of the team includes developing the next generation NPU architecture performance model and conducting performance analysis using models from various benchmarking suites or customer end-to-end use cases.
The role’s responsibilities include but are not limited to:
- Define performance model architecture and modeling flow to best reflect the interworking of NPU SW/HW.
- Implementing and testing performance models with systematic SW development practice.
- Conduct performance-and-power analysis of various neural network workloads.
- Utilize the performance data-driven flow to drive the NPU architecture definition.
- Collaborates with management, product owners, and project managers to evaluate feasibility of requirements and determine priorities for development.
- Performs pathfinding, surveys technologies, participates in standards committees, and presents at external and internal events.
- May interact with multiple technologists in the company to influence architectures and optimize/customize software offerings.
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications could be obtained through a combination of schoolwork, classes, research, and/or relevant previous job and/or internship experiences.
Minimum Qualifications
- Bachelor's Degree in Electrical Engineering, Computer Engineering, or Computer Science or related engineering field with 6 years of relevant experience – OR – Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science or related engineering field with 4 years of relevant experience – OR – PhD in Electrical Engineering, Computer Engineering/Computer Science with 2 years of relevant experience, or related engineering field
- 6 years of experience in two or more of the following:
- Knowledge of computer architecture concepts such as pipelining, caching, parallel computing with SIMD/VLIW, multi-core/multi-threading, data precision, memory hierarchy
- Understanding HW modeling concepts such as event-driven, concurrency, etc.
- Knowledge of AI framework, AI models and basic neural computing operations.
- Knowledge of data precision, floating point vs fixed point computing trade-offs.
- Experiences for object-oriented programming in C/C or Python. Capable of design class objects, data structure and API methods are required.
- Prior usage of event-driven modeling language (SC/C /Python) and platforms
- Prior experience in architecture definition and/or mentoring junior engineers is highly desirable.
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro, US, Oregon, Portland
Business Group
The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $170,500.00 - 315,490.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
Salary : $170,500 - $315,490