Senior Robotics Middleware Engineer

Location/Eligibility: This is a contract position based in Massachusetts. You must be able to commute to the Wilmington area onsite at least 3 days a week. For this contract, there is no visa sponsorship available.

We are seeking a high-caliber Senior Robotics Middleware Engineer to evaluate, prototype, and build our next-generation communication infrastructure. In this role, you will move beneath the standard application layer to optimize high-throughput, shared-memory messaging on NVIDIA Jetson-class hardware. You will be the architect responsible for eliminating communication bottlenecks, ensuring that heavy ML inference and sensor streams flow through the robot's "nervous system" with zero latency.

Core Responsibilities

• Next-Gen Middleware Evaluation: Lead a comprehensive build-vs-adopt evaluation of Zenoh as a robotics transport layer, analyzing its performance both standalone and as an RMW layer under ROS 2. Deliver architectural recommendations backed by rigorous benchmarks.
• Data Path Optimization: Optimize zero-copy and shared-memory messaging paths on ARM/Jetson architectures, focusing heavily on memory layout optimization, serialization efficiency, and transport tuning.
• Performance Benchmarking: Design and execute benchmarking suites to measure latency, throughput, and CPU/GPU overhead, systematically comparing new architectures against our current data path.
• ML & Sensor Integration: Support the full-stack team by ensuring low-latency integration for heavy workloads, including vision sensors (Stereo/RGBD), IMUs, and ML model inference pipelines (PyTorch, TensorRT, JIT).

Technical Requirements (Must-Have)

• ROS 2 & DDS Internals: Deep, hands-on experience with ROS 2 middleware (RMW) layers and the inner workings of DDS implementations (e.g., Cyclone DDS, Fast DDS).
• Advanced Transports: Proven experience with Zenoh or comparable modern pub/sub architectures designed for high-performance edge computing (e.g., eCAL, iceoryx).
• Systems Programming: Exceptional proficiency in Modern C and deep familiarity with shared-memory Inter-Process Communication (IPC).
• Embedded Profiling: Hands-on experience with performance profiling and bottleneck identification on embedded Linux and ARM architectures.
• Core Languages: Strong proficiency in Python is required alongside your primary C systems skill set.

Preferred Qualifications (Nice-to-Have)

• NVIDIA Jetson Ecosystem: Direct experience optimizing software for Jetson-class hardware.
• Hardware-Aware Memory: Understanding of GPU/CUDA memory awareness, unified memory architectures, and avoiding host-to-device copy overhead.
• Real-Time Systems: Practical knowledge of real-time Linux patches (PREEMPT_RT) and deterministic software design.
• Experiencing tuning or customizing the ROS 2 Nav2 stack or working with vSLAM algorithms.

Are you the right fit?

You thrive in high-velocity environments where engineering decisions directly impact hardware performance. You enjoy digging into network packets, memory dumps, and kernel-level timing to squeeze microsecond efficiencies out of resource-constrained systems. You value data over assumptions and back up your architectural designs with hard benchmarks.