Verification Engineer

Job Title: Verification Engineer

Work Location: Longmont, CO - 100% onsite initially; open to hybrid option after a trial period

Job Duties:

Participate in design and functional verification of a block(s) of IP. In this role you will be part of a PCIe development and productization team. A majority of the verification will target PCIe device testing DMA, CXL, IDE, VIP models, traffic generators/checkers, etc.

EXPERIENCE:

• 3 or more years of verification experience with SystemVerilog for IP or system level verification; a particular focus being deep testbench creation experience and/or agent (AKA BFM) development
• Familiar with UVM verification methodologies
• Strong debug skills with simulation tools like QuestaSim, VCS, or Xcelium
• Write scripts quickly for task automation or result summaries: Python, Bash, Perl, TCL, etc.
• High speed IO familiarity like Ethernet, PCIe, CXL
• Familiar with ASIC or FPGA bring-up after chip tapeout
• Strong analytical skills and attention to detail
• Excellent written and communication skills
• Familiarity with PCIe and serial protocols is a bonus

Nice-to-have skills:

• FPGA Experience (Xilinx/AMD FPGA preferred), Vivado experience
• Design creation with AMD Vivado toolchain; familiarity with various AMD IPs
• Linux kernel debugging experience
• Experience with licensed verification IP (VIP) from Siemens, Cadence, or Synopsys