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FPGA Engineer job opportunity at Tucson, AZ

Indotronix International Corp
Tucson, AZ Contractor
POSTED ON 8/15/2026
AVAILABLE BEFORE 9/13/2026
Indotronix is seeking a FPGA Engineer (P4) – MAT Ramp for a job opportunity in Tucson, AZ.
 
Job Title: MAT Ramp: FPGA Engineer - P4 
Location: Tucson, AZ 85756
Duration: 12 Months Contract
Pay Rate: $116/hr on W2
Shift: 1st shift - 9/80A schedule
 
Note: Need Active security clearance
 
Job Description
FPGA Engineers develop and verify designs for all major FPGA vendors and device families including: Xilinx, Altera, and Microsemi. Designs are implemented using VHDL for the following applications: gigabit serial interfaces, Radio Frequency (RF) and Electro Optical (EO) DSP, controls, data links, embedded processing and processor interfaces. Designers work with circuit card designers and systems engineers to develop requirements, architect new parts, collaborative modeling of algorithms, code development, simulation, and place and route. Designs are verified against requirements and design support is expected from requirements definition through integration and test.
 
Qualifications You Must Have:
Minimum 8 years of experience to include at least 1 of the following: 
Digital design and VHDL coding 
Xilinx or Microsemi devices and flow tools 
Delivering FPGA solutions to system level applications 
Hands on experience with integration and debug 
Desired - FPGA design experience in one or more of the following areas: 
Radar processing techniques 
Image processing techniques for visual and infrared sensors 
Embedded systems design using ARM, Microblaze, or Nios processors 
Gigabit serial interfaces and multi-gigabit transceivers (MGTs) 
Constrained random verification in UVM using System Verilog 
Verification utilizing emulation platforms, such as Veloce  
Day to day - Design and deliver production quality FPGA releases from initial proof of concept up to production 
Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS) 
Translate system level requirements into FPGA requirements 
Design and code in VHDL for reliability and maintainability 
Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage 
Help drive projects and execute to program schedules on time and budget 
Create complete documentation including requirements, verification plan, and user’s guides 
May support internal and external technical reviews has context menu

Salary : $105 - $116

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