What are the responsibilities and job description for the Senior IC Layout Engineer position at IC Resources?
We’re looking for a Senior IC Layout Engineer for one of our leading Semiconductor clients based in Reading, Berkshire. If you are looking to broaden your experience within a high growth, internationally recognised semiconductor company, this could be the role for you!
As the Senior IC Layout Engineer you will own the custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed SerDes up to and beyond 28Gb/s and/or memory IO in advanced semiconductor technology nodes. You will have the opportunity to lead chip layout activities; hence there’s a lot of scope for career progression and satisfaction as you see your work in the final product.
As the ideal candidate you will be an experienced Analog IC Layout Engineer, ideally a background working on high speed designs.
Experience is required in some or all of the following;
Take the next step in your career—contact Caroline Pye today for more details or to apply.
As the Senior IC Layout Engineer you will own the custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed SerDes up to and beyond 28Gb/s and/or memory IO in advanced semiconductor technology nodes. You will have the opportunity to lead chip layout activities; hence there’s a lot of scope for career progression and satisfaction as you see your work in the final product.
As the ideal candidate you will be an experienced Analog IC Layout Engineer, ideally a background working on high speed designs.
Experience is required in some or all of the following;
- Custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or high frequency circuits
- Layout of high-speed or high frequency circuits such as ,amplifiers, oscillators, phase-locked loops, delay-locked loops, biasing, buffers, regulators, filters, data converters
- Layout approaches and techniques for high-speed circuits, matching constraints, minimisation of parasitics, power grids and ESD requirements
- Modern semiconductor process technologies including 28nm, 14/16nm, 7nm
- EDA tools for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop, ESD, etc
Take the next step in your career—contact Caroline Pye today for more details or to apply.