What are the responsibilities and job description for the Formal Verification Engineer position at HIKINEX?
WHAT YOU'LL DO :Define comprehensive formal verification plans, strategies, and methods for a high-quality verification sign-offReview and aid in developing the RTL design architecture and specificationProve functional correctness of design features using formal verification methods like model checking, logical equivalence checking, or theorem provingFormal sign-off delivering high quality IP or block in conjunction with simulation-based methodology for overall verification closureDevelop and maintain regressions, tools, infrastructure, and integrated formal and functional verification methodologyWHAT YOU'LL BRING :Degree in Electrical, Computer Science, Computer Engineering or equivalent experience5 years of work experience in verifying complex hardware systems using model checking or logical equivalence checking formal methodsExperience with interactive theorem proving is a plusSolid programming skills in Verilog, System Verilog, SVA or PSL, and any scripting language like Tcl, Python, or PerlProficient in debugging CPU, GPU, fabric, NOC, memory, various protocols like PCIE or Ethernet, or other complex ASIC designsKnowledge of advanced computer architecture and micro-architecture concepts
Salary : $159,900