TITLE:                         SR. PLATING PROCESS DEVELOPMENT ENGINEER

FLSA STATUS:            EXEMPT

REPORTS TO:             DIRETOR, PLATING PROCESS DEVELOPMENT

SUMMARY:

Under the direction of the Director of Plating Process Development, the Sr. Plating Process Development Engineer is responsible for developing and delivering new strategies for improving and optimizing plating  and wet etch process and procedures; designing and conducting moderately advanced wafer experiments, analyzing the data, and reporting the results; developing and implementing new practices or methodologies which reduce cost and improve operational efficiency; conducting root cause analysis and implementing corrective action; developing and implementing procedures for transitioning new products into the production line; and reviewing, updating, and maintaining documentation and process instructions. This position is located in Milpitas, California.

ESSENTIAL FUNCTIONS:

• Develops and delivers new strategies for improving and optimizing wafer plating and wet etch processes and procedures
• Develops and implements new practices or methodologies which reduce cost and improve operational efficiency
• Conducts root cause analysis and implements corrective action if required
• Develops and implements processes or procedures for transitioning new products into the production line
• Monitors and sustains prototype wafers to ensure they move through the plating or wet etch process smoothly
• Reviews, updates, and maintains documentation and process instructions
• May instructs operators and technicians on processes and procedures, including modifications to existing procedures
• Partners with equipment and maintenance personnel in order to minimize tool down time and integrate new tools into the production line
• Designs and conducts moderately advanced experiments, analyzes data, and develops recommendations for improving the performance or reducing cost based on test results
• Partners with other groups and departments, including process and product engineering to develop and implement new processes which reduce scrap and improve yield
• Responds to inquiries from other team members, managers, or departments
• Adheres to all safety policies and procedures as required
• Performs other duties of a similar nature or level*

MINIMUM QUALIFICATIONS:

• Master’s degree in Chemical or Electrical Engineering, Materials Science, or Physics, and/or equivalent relevant experience; PhD degree preferred

• Six years of hands’ on experience working in the magnetic recording head, hard disk drive, or semiconductor industry in a thin film plating or process engineering role
• Strong knowledge and experience using JMP, SPC, or similar software
• Proficient in the use of Microsoft Office Applications

Knowledge, Skills, and Abilities:

• Strong knowledge of thin film plating and wet etch development and manufacturing processes, practices, and techniques
• Knowledge of wafer fabrication processing techniques and tools
• Knowledge and ability to use Microsoft Office applications to create spreadsheets, Word documents, and presentations
• Able to design moderately complex experiments, analyze results, and recommend corrective action in order to reduce scrap and improve yield
• Able to communicate effectively, both verbally and in writing, with all levels of contractors, consultants, employees, and management
• Able to work productively and collaboratively with all levels of employees and management
• Able to comply with all safety policies and procedures
• Demonstrated organizational and time management skills
• Demonstrated problem-solving and trouble shooting skills
• Flexible and able to prioritize

The annual base salary for this full-time position is between $127,967.46-$188,187.44 bonus target benefits. Within the range the individual pay may differ depending on additional factors including job responsibilities, job related knowledge, skills, abilities, education, and experience. The annual base pay range shown is subject to change and may be modified periodically.

WORKING CONDITIONS:

The Sr. Plating Process Development Engineer works primarily in an office environment from Monday thru Friday.  The schedule may be altered from time-to-time to meet business or operational needs; may travel from building-to-building as needed.  May also work in a class 100 ESD sensitive wafer fab manufacturing facility; adheres to required safety and dress standards. May be exposed to hazardous chemicals, fumes, or vapors and excessive noise from time-to-time while in the wafer manufacturing facility; stands and walks; performs various fine grasping movements, bends, and twists; operates a computer and enters information using a keyboard, operates a telephone, and other office equipment. May occasionally be required to push, pull, or lift 10 or more pounds.

*Other duties of a similar nature or level are duties that may be required, but may not be specifically listed in the job description or posting.

TDK/Headway Technologies, Inc. provides equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, gender, national origin, age, disability, or genetics. Applicants requiring accommodation in order to complete the application process should contact the Headway Human Resources Department.

Salary : $127,967 - $188,187