FPGA Verification Engineer

Position Title: FPGA Verification Engineer

Location: Mountain View, CA
Duration: 6 Months

Job Description:

We are seeking a highly skilled FPGA Verification Engineer to join our engineering team. The ideal candidate will have hands-on experience in FPGA design verification, strong knowledge of SystemVerilog, and expertise in UVM methodologies. This role involves working closely with design and development teams to ensure the functionality, performance, and reliability of FPGA-based systems.

Key Responsibilities:

• Develop and execute verification plans for FPGA-based designs.
• Utilize SystemVerilog and UVM for testbench development and verification.
• Perform code coverage and functional coverage analysis to ensure verification completeness.
• Debug and resolve design and verification issues efficiently.
• Collaborate with cross-functional teams to achieve design verification goals.
• Work with industry-standard tools such as QuestaSim and Synopsys VCS.

Required Skills & Qualifications:

• Strong understanding of FPGA design principles and architectures.
• Proficiency in SystemVerilog and UVM verification methodology.
• Experience with verification tools like QuestaSim or Synopsys VCS.
• Knowledge of code coverage and functional coverage analysis.
• Excellent debugging, problem-solving, and collaboration skills.

Education & Experience:

• Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or a related field.
• Proven experience in FPGA verification.
• Experience with scripting languages such as Python or Perl.
• Familiarity with hardware description languages (HDLs) such as VHDL and Verilog.