IC Design Engineer (Senior, Staff or Principal - up to $580k TC)

RTL IC Design Engineer (Senior, Staff or Principal)

Compensation:

For Senior - up to approx $280k total comp ($120-160k base, 20% bonus RSUs)

For Staff - up to approx $400k total comp ($150-190k base, 25% bonus RSUs)

For Principal - up to approx $580k total comp ($180-240k base, 30% bonus RSUs)

Shape the Future of AI Infrastructure

Join an industry-leading engineering team developing the high-performance silicon that powers next-generation AI, machine learning, cloud computing, and hyperscale data center infrastructure. This is an opportunity to work on complex, cutting-edge ASIC designs that sit at the heart of some of the world's most demanding computing environments.

If you are passionate about digital design and want to see your work directly influence the future of AI and high-speed connectivity, this role offers the chance to make a meaningful impact while working alongside some of the best engineers in the industry.

The Role

As a Digital IC Design Engineer, you will play a key role in the architecture, design, implementation, and validation of advanced semiconductor products. You will own critical RTL development efforts, collaborate across engineering disciplines, and help bring innovative silicon solutions from concept through production.

This position is ideal for engineers who enjoy solving challenging technical problems, developing highly optimized designs, and working on products that push the boundaries of performance and scale.

Responsibilities

• Analyze architecture specifications and participate in technical reviews.
• Develop microarchitecture and detailed design documentation.
• Design and implement high-performance RTL using Verilog/SystemVerilog.
• Develop complex digital logic including clock domain crossings, pipelined architectures, low-power designs, multi-clock and multi-power domain solutions, and third-party IP integration.
• Drive RTL optimization efforts to achieve timing, power, and performance goals.
• Debug and resolve complex design issues throughout the development cycle.
• Partner closely with verification, firmware, software, emulation, and validation teams.
• Support silicon bring-up and post-silicon validation activities in the lab.
• Contribute throughout the full ASIC development lifecycle.

Required Skills

• Strong Digital IC Design experience.
• Expertise in Verilog and/or SystemVerilog RTL development.
• Experience designing ASICs or complex SoCs.
• Strong understanding of microarchitecture development and RTL design methodologies.
• Experience driving designs through timing closure.
• Excellent debugging, analysis, and problem-solving skills.
• Ability to collaborate effectively in a fast-paced engineering environment.

Nice To Have Skills

• PCIe protocol experience.
• CXL protocol knowledge.
• Familiarity with AMBA protocols (AXI, AHB, APB).
• Experience with PCIe switch architectures.
• Experience with storage, RAID, or high-performance data movement solutions.

Why Join Us?

• Work on technology that enables next-generation AI and machine learning infrastructure.
• Tackle highly complex engineering challenges at massive scale.
• Be part of a team building products deployed in some of the world's largest data centers.
• Collaborate with top-tier engineers in a highly technical, innovation-driven environment.
• Gain exposure across architecture, RTL design, silicon bring-up, and product validation.
• Take ownership of meaningful technical work with visible impact.
• Enjoy significant opportunities for technical growth, career advancement, and long-term development.

This is a unique opportunity to help build the silicon foundation powering the future of AI, cloud computing, and next-generation data center technologies.