Senior Design Verification Engineer

Job Title: Senior ASIC Design Verification Engineer

Duration: 12 months with possible extension

Location: San Diego, CA

Job Summary:

We are seeking a Senior ASIC Design Verification Engineer to verify high-speed mixed-signal IPs used in cutting-edge products for 5G, AI/ML, compute, IoT, and automotive applications.

This role involves end-to-end ownership of the verification lifecycle, including pre-silicon verification, coverage closure, gate-level simulation, and post-silicon support. The ideal candidate is highly hands-on, experienced with SystemVerilog/UVM, and has exposure to industry-standard high-speed interfaces.

Key Responsibilities:

• Develop and execute pre-silicon and post-silicon verification test plans based on design specifications and industry standards.
• Architect and implement advanced verification environments using SystemVerilog and UVM.
• Create and maintain UVM testbenches, test sequences, scoreboards, and monitors.
• Write and debug SystemVerilog Assertions (SVA).
• Develop functional and code coverage models and drive coverage closure.
• Perform gate-level simulations, low-power verification, and formal verification as required.
• Collaborate closely with digital design, analog design, modeling, subsystem, and SoC integration teams.
• Support PHY-level verification, subsystem integration, SoC-level verification, and post-silicon validation/debug.
• Contribute to or develop Verification IP (VIP) for SerDes controller PHY (strong plus).

Required Qualifications:

• 2 years of experience in ASIC/IP Design Verification.
• Strong expertise in:
• SystemVerilog
• UVM
• Verilog
• Assertion-Based Verification (SVA)
• Functional and code coverage
• Hands-on experience with ASIC simulation tools such as:
• VCS, Xcelium/NCsim, Questa/Modelsim
• Formal tools (JasperGold, VC Formal, 0-In) preferred
• Solid understanding of ASIC verification methodologies and flows.

Education:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

Preferred / Nice-to-Have Skills

• Experience with low-power verification (UPF/CPF).
• Experience with formal verification and gate-level simulation.
• Knowledge of high-speed and standard protocols such as:
• PCIe, USB, MIPI, DDR/LPDDR, CXL, UFS
• Exposure to mixed-signal IP verification, including:
• SerDes, PHYs, PLLs, ADCs, DACs, sensors
• Scripting experience using Python or Perl.
• Familiarity with Jira, SharePoint, Tableau, or similar tools.
• Strong documentation and reporting skills (Excel, Word, PowerPoint).

Enterprise Solutions Inc. is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.