Design Verification Engineer

Job Title: Design Verification Engineer

Duration: 12 Months

Location: San Diego, CA

Job Description:

Design verification team in verifying the high-speed mixed-signal IP designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support.

Responsibilities:

• Define pre-silicon and post-silicon test plans based on design specs and using applicable standards, working closely with the design team.
• Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality.
• Author assertions in SVA, develop testcases, coverage models, debug, and ensure coverage closure.
• Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation.
• From scratch VIP development experience for Serdes controller PHY is an additional plus

Preferred Qualifications:

• Experience with low-power design verification, Formal verification, and gate-level simulation.
• Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc..
• Experience in scripting languages (Python or Perl).
• Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Converters (DAC, ADC), or sensors.

Top 5 Required Skills:

• Knowledge of a HVL methodology like SystemVerilog/UVM.
• Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In, and others.
• Protocol knowledge of High Speed Serdes external interfaces like PCIe, USB3/4, UFS, MIPI CSI/DSI/HDMI, and DDR PHY
• It would be a plus if the candidate has working experience on UPF-based power-aware simulations and gate-level simulations
• Good at implementing system Verilog assertions and checkers, good debugging skills

Technologies

• Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc.

Education Requirement

• Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field

Required Years of Experience

• 5 years ASIC design verification, or related work experience.

Enterprise Solutions Inc. is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.