What are the responsibilities and job description for the Sr Design Verification Engineer ( Irvine CA - Onsite) position at Encore Semi, Inc.?
Sr Design Verification Engineer (Remote)
Full-time: Salary Benefits Bonuses / Contractor
Work Status: US citizen or Lawful Permanent Resident.
Location: Irvine CA
Digital ASIC Verification Engineer
We are looking for an experienced Digital ASIC Verification Engineer to verify complex digital systems, including ARM-based CPUs and DSP blocks. You will own the full verification lifecycle, from test planning to coverage closure using SystemVerilog and UVM.
Responsibilities
Full-Time Benefits
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
LinkedIn :: https://www.linkedin.com/in/rtl2gds/
Full-time: Salary Benefits Bonuses / Contractor
Work Status: US citizen or Lawful Permanent Resident.
Location: Irvine CA
Digital ASIC Verification Engineer
We are looking for an experienced Digital ASIC Verification Engineer to verify complex digital systems, including ARM-based CPUs and DSP blocks. You will own the full verification lifecycle, from test planning to coverage closure using SystemVerilog and UVM.
Responsibilities
- Develop UVM/SystemVerilog testbenches for block and system-level verification
- Create and execute test plans; drive functional and code coverage closure
- Automate test generation and regressions using Python and MATLAB
- Support pre-silicon verification and post-silicon bring-up
- Collaborate across teams to ensure design quality and integrity
- 10 years of ASIC verification experience
- Strong skills in SystemVerilog, UVM, and constrained random verification
- Familiarity with ARM/CPU architecture and OOP concepts
- Proficiency in Python scripting (MATLAB a plus)
- Bachelors in EE/CS/CE (Master’s preferred)
Full-Time Benefits
- 15 days of PTO per calendar year
- 10 paid Holidays per calendar year
- Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
- Dental & Vision: Company covers 50% of premiums for Employee and Dependents
- Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
- Employee Assistant Program (EAP)
- 401k - Traditional & Roth
- Life/AD&D and Long-Term Disability
- Tuition reimbursement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
LinkedIn :: https://www.linkedin.com/in/rtl2gds/
Salary : $150,000 - $165,000