What are the responsibilities and job description for the Design Verification Engineer position at E-Solutions, Inc.?
Position: Design Verification Engineer
Type/Duration: Full time//Permanent
Location: San Jose, CA (5 Days onsite in a week)
Summary:
We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.
Key Responsibilities:
- Develop and maintain UVM-based verification environments
- Create test plans, testcases, and coverage models
- Perform functional verification of RTL designs
- Debug RTL and testbench issues
- Drive coverage closure (functional code)
Required Skills:
- Strong hands-on with SystemVerilog and UVM
- Experience in block-level verification
- Good understanding of digital design fundamentals
- Experience with debug tools (Verdi, DVE, etc.)
Good to Have:
Exposure to low-power verification (UPF)
Experience with AMBA protocols (AXI/AHB/APB)
Design Verification Engineer1design,Verification,UVM,Verilog,RTLN/AFull TimeUnited States