What are the responsibilities and job description for the Principal Hardware Architect & Engineering Manager position at Delphi Engineering Group?
Title: Principal Hardware Architect & Engineering Manager
Location: Irvine, CA
Employment Type: Full-time
Reports To: CEO / Executive Leadership
Company: Delphi Engineering Group
Role Summary
The Principal Hardware Architect & Engineering Manager is the senior technical and execution authority for DEG’s FPGA-based hardware platforms. This role combines hands-on hardware architecture and board-level design with direct management of the hardware and FPGA engineering function.
This position owns:
- Hardware system architecture
- Board-level design integrity
- Hardware ↔ FPGA integration
- Engineering execution, priorities, and delivery
This is not a pure people-management role and not a layout-only role. It is a hands-on technical leadership position with real accountability.
Core Responsibilities
System & Hardware Architecture
- Define system-level hardware architecture for: (1) PCIe, FMC/FMC , and VPX platforms, and (2) High-speed data acquisition and playback systems
- Select and qualify key technologies: (1) AMD/Xilinx FPGAs (device and interface selection), (2) High-speed ADCs/DACs (JESD204B/C), and (3) Clocking, synchronization, and trigger subsystems
- Define PCIe Gen4/Gen5 hardware architecture and throughput strategy
- Establish hardware design standards reused across product families
- Own technical tradeoffs involving performance, risk, cost, and schedule
Board-Level Hardware Design
- Own complete board designs from concept through production release
- Drive schematic capture for: (1) FPGA subsystems and I/O, (2) High-speed serial interfaces, (3) Memory (DDR, HBM where applicable), and (4) Power, clocking, reset, and configuration
- Define PCB stackups, routing constraints, and SI/PI requirements
- Work directly with PCB designers to ensure correct implementation
- Lead board bring-up, debug, and validation
- Resolve cross-discipline hardware issues (hardware ↔ FPGA ↔ test)
FPGA Architecture & Integration (Oversight Level)
- Define FPGA-facing hardware architecture, including: (1) JESD204B/C link topology, (2) Clock domain and synchronization concepts, (3) Reset and configuration strategy, and (4) PCIe interface expectations
- Review FPGA designs for hardware compatibility and system correctness
- Collaborate with FPGA engineers on interface definition and partitioning
- Ensure hardware designs support FPGA timing, clocking, and throughput needs
This role requires architectural understanding of FPGA systems, not day-to-day RTL development.
Engineering Management & Execution
- Directly manage hardware and FPGA engineers (employees and contractors)
- Own engineering priorities, schedules, and resource allocation
- Balance new development, sustaining engineering, and customer-driven work
- Lead design reviews, release decisions, and technical risk assessments
- Set expectations for design quality, documentation, and release discipline
- Coordinate engineering work across hardware, FPGA, software, and test
- Act as the escalation point for technical and execution issues
Technical Leadership & External Interface
- Serve as the final technical authority for hardware decisions
- Mentor engineers and enforce engineering standards
- Interface with customers on deep technical topics when required
- Support proposal development and technical responses
- Preserve technical continuity across product generations
Required Qualifications
- 15 years experience in complex digital and mixed-signal hardware design
- Proven ownership of complete board designs
- Demonstrated experience leading engineering teams or technical groups
- Deep expertise in: (1) High-speed digital interfaces (PCIe, SERDES), (2) JESD204B/C-based converter systems, and (3) Clocking, synchronization, and power architecture
- Working knowledge of FPGA architecture sufficient to guide integration
- Strong bring-up and debug experience
- Comfortable making final technical and execution decisions
- U.S. Person (citizenship or permanent residency)
Preferred Experience
- AMD/Xilinx UltraScale or Versal platforms
- FMC / FMC / VPX carrier designs
- Wideband ADC/DAC or Direct RF systems
- Defense or aerospace programs
- Small-team, high-ownership environments