Senior Principal Engineer(Hardware Application Engineering ) at Greensboro, NC (ONSITE)

Job Title: Senior Principal Engineer

Location: Santa Clara, CA (ONSITE)

Duration: Fulltime

What We're Looking For

PhD, Master's, or Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
15 years of experience in hardware design, development, and validation of high-speed networking or compute systems.
7 years of dedicated experience in board and system design for high-speed platforms involving modern SerDes (25G NRZ through 112G/224G PAM4).
Proven full-lifecycle ownership of complex high-speed boards: architecture, schematic, layout guidance, and bring-up.
Demonstrated experience defining and delivering reference designs that enabled customer or internal platform adoption.
Strong expertise in PCB stack-up design and material selection for high-speed, high-layer-count boards.
Deep experience with power architecture for high-current ASICs, including PDN design, sequencing, decoupling, and tolerance analysis.
Solid background in thermal design and mechanical integration for high-power network and AI systems.
Working knowledge of SI/PI principles, with the ability to review customer simulations and run targeted simulations independently when needed.
Hands-on experience with hardware bring-up, lab debug, and root-cause analysis using industry-standard lab equipment.
Deep understanding of high-speed interfaces: Ethernet, PCIe, DDR, advanced SerDes, and modern power delivery architectures.
Strong grasp of design for reliability, manufacturability, and testability across the product lifecycle.
Customer-facing experience supporting complex technical engagements and resolving real-world deployment issues.
Proven ability to develop and deliver technical training content to engineering audiences.
Excellent communication skills, with the ability to influence senior customer engineering teams and collaborate across disciplines and geographies.

Preferred

Direct experience with Ethernet switch platforms (any tier) and/or emerging open AI fabric standards and architectures.
Experience designing or reviewing platforms targeting megascale data center deployments.
Background in reference platform design and customer enablement for silicon-based solutions.
Familiarity with ODM/CM manufacturing flows, including DFM/DFT, qualification, and reliability testing.
Experience with advanced cooling approaches (liquid, immersion) for high-power AI/networking platforms.
EDA tool fluency in either Cadence (Allegro/Sigrity) or Mentor/Siemens (Xpedition/HyperLynx) ecosystems - tool-agnostic candidates with deep expertise welcome.
Track record of influencing silicon and platform roadmaps based on customer and field insights.