What are the responsibilities and job description for the Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement position at Data Capital Inc?
Job Details
Mandate Skills:
FPGA
Verification Exp
Strong SystemVerilog coding
(Universal Verification Methodology)-UVM
- 5 years of FPGA verification experience
- Strong SystemVerilog programming skills
- Hands-on experience with UVM (Universal Verification Methodology)
- Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS)
- Experience with code and functional coverage analysis
- Proficient in debugging and problem-solving
- Scripting experience in Python or Perl
- Knowledge of Verilog and/or VHDL
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