What are the responsibilities and job description for the Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6 position at Comprehensive Resources Inc.?
Verification Lead / Principal Verification Engineer - PCIe Gen5/Gen6
Location: San Jose, CA
Experience: 10 Years
Job Type: Contract / Long-Term
Job Summary
We are seeking a Verification Lead / Principal Verification Engineer with strong hands-on experience in PCIe Gen5/Gen6 verification to lead end-to-end verification of PCIe Controller and Subsystem IP.
The ideal candidate will have deep expertise in PCIe protocol, UVM, SystemVerilog, LTSSM, PIPE, PHY/SerDes, assertions, coverage closure, emulation, and protocol compliance.
Responsibilities
- Own PCIe Gen5/Gen6 verification strategy, planning, execution, and signoff.
- Review PCIe architecture, microarchitecture, specifications, and RTL.
- Develop and architect reusable UVM-based verification environments.
- Verify PCIe Transaction Layer, Data Link Layer, Physical Layer, and PIPE interfaces.
- Develop test plans, testcases, scoreboards, assertions, and coverage models.
- Verify LTSSM, link training, equalization, recovery, speed changes, and lane-width changes.
- Verify Controller-to-PHY integration and PCIe protocol compliance.
- Drive functional, code, assertion, and cross-coverage closure.
- Support IP, subsystem, and SoC-level verification.
- Support emulation, post-silicon debug, and silicon validation.
- Lead and mentor verification engineers.
- Collaborate with Architecture, RTL Design, DFT, Firmware, Physical Design, PHY, and Validation teams.
Required Skills
- 10 years of ASIC/SoC Design Verification experience.
- Strong hands-on PCIe Gen5/Gen6 verification experience.
- Deep understanding of PCIe Transaction, Data Link, and Physical Layers.
- Strong knowledge of LTSSM, PIPE, link training, equalization, and recovery.
- Expert-level SystemVerilog and UVM.
- Strong SVA/assertion-based verification experience.
- Functional, code, assertion, and cross-coverage experience.
- PCIe Controller-to-PHY/SerDes integration experience.
- SR-IOV and advanced PCIe features preferred.
- Emulation experience with Veloce, Palladium, or ZeBu preferred.
- Strong technical leadership and communication skills.
Education
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Electronics Engineering, or related field.
To Apply: Please send your updated resume to .