What are the responsibilities and job description for the Hiring - Physical Design Engineer in Santa Clara, CA position at CaritaTech LLC.?
Hi,
Role: Physical Design Engineer
Location: Santa Clara, CA
Work mode: 5 Days Onsite
Location: Santa Clara, CA
Work mode: 5 Days Onsite
Fulltime and W2 contracts
Any Visa is workable
Any Visa is workable
Total 10 positions available, covering all experience levels from Junior to Senior.
*Experience:* 4 15 Years
Key Responsibilities
* Execute end-to-end physical design implementation including:
* Floorplanning
* Power grid design
* Placement & Routing
* Clock Tree Synthesis (CTS)
* Timing Closure
* Signal/Power Integrity Signoff
* Physical Verification (DRC/LVS/Antenna)
* EM/IR Analysis
* DFM Closure
* Perform full-chip and block-level timing analysis and provide optimization guidance to subsystem/block owners.
* Work on advanced low-power and high-performance SoC designs.
* Drive design convergence and signoff closure across multiple implementation stages.
* Collaborate with cross-functional teams including RTL, STA, DFT, and Signoff.
Required Skills
* Strong hands-on experience with Cadence and Synopsys EDA tool suites.
* Expertise in STA and timing signoff using Synopsys PrimeTime.
* Experience handling large block/subsystem/full-chip implementation.
* Strong scripting knowledge in TCL, Perl, Shell, and Make flows.
* Good understanding of advanced technology nodes including 7nm/5nm/3nm.
* Strong debugging, analytical, and communication skills.
* Self-driven and capable of driving new methodologies and automation.
Qualifications
Bachelor's or Master's degree in Electronics / VLSI / Electrical Engineering.
*Experience:* 4 15 Years
Key Responsibilities
* Execute end-to-end physical design implementation including:
* Floorplanning
* Power grid design
* Placement & Routing
* Clock Tree Synthesis (CTS)
* Timing Closure
* Signal/Power Integrity Signoff
* Physical Verification (DRC/LVS/Antenna)
* EM/IR Analysis
* DFM Closure
* Perform full-chip and block-level timing analysis and provide optimization guidance to subsystem/block owners.
* Work on advanced low-power and high-performance SoC designs.
* Drive design convergence and signoff closure across multiple implementation stages.
* Collaborate with cross-functional teams including RTL, STA, DFT, and Signoff.
Required Skills
* Strong hands-on experience with Cadence and Synopsys EDA tool suites.
* Expertise in STA and timing signoff using Synopsys PrimeTime.
* Experience handling large block/subsystem/full-chip implementation.
* Strong scripting knowledge in TCL, Perl, Shell, and Make flows.
* Good understanding of advanced technology nodes including 7nm/5nm/3nm.
* Strong debugging, analytical, and communication skills.
* Self-driven and capable of driving new methodologies and automation.
Qualifications
Bachelor's or Master's degree in Electronics / VLSI / Electrical Engineering.