What are the responsibilities and job description for the SoC Verification Engineer position at Canvendor?
Job Title: Senior SoC Verification Engineer (UVM)
Location: Chandler, Arizona.
Experience: 6 years
Role Overview
We are seeking a Senior SoC Verification Engineer with strong expertise in UVM-based environments to join our growing verification team . The ideal candidate will have extensive hands-on experience in SoC-level verification, testbench architecture, and debug using industry-standard EDA tools.
Key Responsibilities
- Develop and maintain UVM-based verification environments for complex SoC projects.
- Create comprehensive test plans, implement test cases, and ensure coverage closure.
- Debug RTL and testbench failures using industry-standard simulators.
- Collaborate closely with design, architecture, and firmware teams to ensure verification completeness.
- Drive verification strategy from block-level to SoC-level integration.
- Perform functional coverage analysis, assertion-based verification (SVA), and regression management.
- Support post-silicon validation and bring-up activities as required.
Required Skills & Experience
- 6 years of experience in ASIC/SoC verification.
- Strong hands-on experience with SystemVerilog and UVM methodology.
- Proficiency in testbench architecture, stimulus generation, and scoreboard implementation.
- Experience with major EDA tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
- Solid understanding of AMBA protocols (AXI/AHB/APB) and on-chip interconnects.
- Familiarity with C/C and scripting languages (Python/Perl/Shell).
- Strong debug and problem-solving skills.
- Excellent communication and teamwork abilities.
Education
- B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or Computer Engineering.