Principal Engineer, Digital Verification and Emulation

• Lead hardware-assisted verification using emulation platforms such as Synopsys ZeBu, Cadence Palladium, Siemens Veloce, or equivalent.
• Own emulator bring-up, compile/debug flows, model mapping, debug visibility, runtime optimization, and emulation regression execution.
• Build reusable verification environments for complex IP blocks, subsystems, and SoC-level designs using SystemVerilog, checkers, monitors, scoreboards, transactors, memory models, bus-functional models, and emulation-ready test infrastructure.
• Adapt simulation environments for emulation and acceleration, including synthesizable components, test migration, and emulator-friendly verification methodology.
• Develop, integrate, and validate real-number models, behavioral models, and mixed-signal abstraction models for analog/digital interface verification.
• Partner with firmware and software teams to run pre-silicon workloads, diagnostics, register tests, traffic generation, and long-running system scenarios on emulation platforms.
• Collaborate with architects and RTL designers to define verification plans, identify design risks, improve testability, and ensure readiness for simulation, emulation, and tape-out.
• Debug complex failures across RTL, verification infrastructure, emulation models, firmware, embedded software, and mixed-signal behavioral models.
• Define and track functional coverage, code coverage, assertions, verification metrics, exclusions, waivers, and signoff criteria.
• Use assertions and formal techniques selectively for control logic, interfaces, reset behavior, CDC/RDC-sensitive logic, and difficult corner cases.
• Develop scripts, flows, dashboards, and automation for regressions, emulation builds, job scheduling, log analysis, performance tracking, and coverage reporting.
• Mentor engineers, conduct technical reviews, and drive verification methodology across the team.

• BS in Electrical Engineering, Computer Engineering, or related field with 12 years of relevant ASIC/SoC verification experience, or equivalent experience.
• 6 years of hands-on experience with hardware emulation or acceleration platforms such as Synopsys ZeBu, Cadence Palladium, Siemens Veloce, or equivalent. Experience should include bringing up complex digital designs in emulation, debugging emulation builds, migrating simulation tests to emulation, supporting long-running workloads, improving debug visibility, and working with emulation-ready components such as transactors, checkers, memory models, and bus-functional models.
• 12 years of digital verification experience across complex IP, subsystem, or SoC-level designs, from verification planning through debug, coverage, and signoff closure. Strong SystemVerilog skills are required; familiarity with UVM is expected, but this role is not limited to UVM testbench development. Experience with real-number models, behavioral models, mixed-signal abstraction models, assertions, or selective use of formal techniques is highly valuable.
• Strong coding and automation skills using Python, Tcl, Perl, Shell, Make, or similar tools. Experience developing verification flows, regression automation, emulation build scripts, log analysis tools, coverage reporting, dashboards, or debug utilities is expected. Experience with C, C , SystemC, Python, or MATLAB models for reference modeling or scoreboarding is a plus.
• Strong hardware understanding, including SoC interfaces and protocols such as AMBA AXI/AHB/APB, PCIe, UCIe, Ethernet, SPI/I2C, memory-mapped buses, or similar high-speed interfaces. Experience with multiple clock domains, reset domains, clock dividers, asynchronous interfaces, CDC/RDC-sensitive logic, firmware interaction, and digital logic that controls or interfaces with analog/mixed-signal blocks is highly desirable.

Salary : $190,000 - $250,000