Process Engineer – Plasma Etch

Avicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications.  This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products.  (www.avicena.tech) 

About The Role

• Responsible for developing, optimizing, and maintaining plasma etching processes used in semiconductor manufacturing.
• Design of Experiments for process performance, yield, and efficiency.
• Responsible for fabrication of components partially between foundry services and in-house wafer fabrication resources.
• Source and manage foundry services, contractors, and vendors.
• Characterize processes and components using semiconductor metrology tools, profilometers, interferometers, SEM, electrical testers and optical testers.
• Work with outside laboratories to characterize processes and devices, conduct failure analyses and model optoelectronic devices.
• Regularly interface with other engineers in Process Engineering and Equipment Engineering.
• Troubleshoot and resolve technical issues with photolithography equipment and processes.
• Indirectly manage engineering technicians and operators.
  
  

Requirements

• BS in Chemical Engineering, Materials Science, Electrical Engineering or a related field.
• 10 years of related industrial experience and managing semiconductor or MEMS foundries.
• Hands-on experience with plasma etch and micro-machining, including strong knowledge of ICP, RIE, DRIE, and wet etching of GaN and silicon.
• Strong knowledge of other MEMS-relevant materials such as sacrificial and structural layers, wet/dry release layers, SU-8, and temporary wafer bonding processes.
• Strong understanding of the effects of film stresses and the management of silicon integrity.
• Strong familiarity with a clean room environment and other semiconductor processing equipment, including contact aligners, steppers, CVD, PVD, ALD, plasma ashing.
• Proficient in Design of Experiments and Statistical Process Control methodologies.
• Extremely organized, data-driven, and detail-oriented, with a strong desire to maintain thorough documentation and a baseline.
• Ability to identify, troubleshoot, and communicate significantly complex engineering problems through documentation and regular presentations to senior and executive staff members.
• Familiarity with health and safety regulations in a cleanroom environment.
  
  

Preferred Requirements

• MS or PhD in Engineering
• 15 years of related industrial experience
• Strong knowledge of semiconductor device physics.
• Proficient with JMP software.
• Proficient with database queries using SQL
• Computer modeling and simulation (optical, thermo-mechanical) desired, but not required.