What are the responsibilities and job description for the ASIC/FPGA Verification Engineer position at Avacend, Inc.?
Job Title: FPGA/ASIC Verification Engineer
Location: San Jose, CA 95128 Hybrid
Contract
Job Description
• Own verification of entire FPGA design used in high-end router products.
• Understand design specifications and interact with design engineers to identify verification scenarios.
• Create test plans, constrained-random verification environments, testcases, regressions, and coverage reports.
• Identify and write all types of coverage measures for stimulus and corner-cases.
Minimum Requirements: (“Must have” Qualifications)
1. Strong academic background in Electrical Engineering (Bachelor's required, Master's preferred)
2. 7-10 years of pure verification experience in ASIC/FPGAs
3. Experience with PCIe, Ethernet, slow speed interfaces like I2C, SPI, MDIO, etc, and developing object-oriented testbench infrastructure, BFMs, and testcases in UVM.
4. Ability to independently develop test plans, test sequences, generate stimuli, and collaborate with RTL designers to debug failures.
Desired Skills/Qualifications/System Experience requirements: (“Nice to have Qualifications”)
1. Experience with scripting languages like Perl, Python is a plus.
2. Proficiency with industry-standard tools, revision control systems, and regression systems.
Salary : $70 - $75