What are the responsibilities and job description for the Field-Programmable Gate Arrays Engineer position at Ateeca Inc?
Job Description:
Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog.
• Develop self-checking and reusable test benches from the ground up, employing Object-Oriented Programming principles such as Inheritance and Polymorphism, while utilizing UVM to build drivers, monitors, predictors, and scoreboards.
A Bachelor of Science degree in Engineering (specializing in Electrical, Mechanical, or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry, or equivalent non-US qualifications relevant to the job description
• Proven experience in ASIC/FPGA verification processes
Proficiency in hardware verification languages, particularly SystemVerilog and SystemVerilog Assertions
Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet)
• Proficient in scripting languages: Make, Perl, Python, etc.
Salary : $75 - $80