Director of Product Engineering

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is seeking a Director of Product Engineering to lead our product engineering organization in San Jose, CA. This is a critical leadership role responsible for driving next-generation high-speed, high-performance, and low-power semiconductor products from silicon bring-up through high-volume manufacturing in advanced process nodes.

As the AI infrastructure market accelerates at an unprecedented pace, Astera Labs needs a seasoned leader who can build and scale a world-class product engineering team while maintaining the technical depth to solve the hardest problems in high-speed connectivity. You will own the complete post-silicon product development lifecycle — from characterization and qualification through production ramp and sustaining — across our portfolio of purpose-built connectivity solutions enabling rack-scale AI.

This role demands a unique combination of hands-on technical expertise in high-speed signaling and ATE test fundamentals, coupled with the organizational leadership to build teams, establish best-known methods, and deliver products to production with uncompromising quality. You'll partner closely with design, validation, operations, and customers to ensure Astera Labs' products set the industry standard for performance and reliability.

Key Responsibilities

• Team Leadership & Organization Building

  • Build, mentor, and lead a high-performing team of product engineers owning a diverse portfolio of connectivity products purpose-built for AI infrastructure
  • Define team strategy, priorities, and execution roadmaps aligned with Astera Labs' aggressive product delivery timelines
  • Establish scalable processes, best-known methods (BKMs), and operational excellence frameworks as the organization grows
  • Make sound technical and organizational decisions in a fast-paced, dynamic environment with competing priorities

• ATE Test Development & Production Excellence

  • Drive ATE test program development and optimization for wafer sort and final test solutions on the Advantest 93K platform
  • Own device ATE test yields, test time reduction, and quality metrics with a detailed, data-driven mindset
  • Establish consistent BKMs for rolling out new ATE test programs across product families
  • Lead data analysis efforts using tools such as JMP or Spotfire to calculate limits, identify outliers, and drive continuous improvement

• Product Qualification & Manufacturing

  • Define and execute standards-based qualification programs at both product and package level
  • Partner with OSATs to support high-volume manufacturing through the complete product lifecycle
  • Ensure seamless production ramp and sustaining operations, delivering quality parts to Astera Labs' hyperscaler and enterprise customers
  • Drive system-level debug involving test hardware, test programs, and DUT interactions across digital and analog domains

• Cross-Functional Technical Leadership

  • Provide technical leadership in high-speed signaling including NRZ/PAM4 SerDes protocols (PCIe Gen 3 , Ethernet 25G ), and memory interfaces such as (LP)DDR5/4
  • Partner with silicon design teams to feed back production learnings and drive DFT/DFM improvements
  • Collaborate with silicon validation teams to ensure device performance meets production requirements
  • Engage with customers and field teams on quality, reliability, and production-related technical matters

Basic Qualifications

• Bachelor's degree in Electrical Engineering or Computer Engineering
• 8 years of experience in post-silicon product development dealing with high-speed signals (product, test, or validation)
• 5 years of managerial experience building and leading product engineering teams
• Hands-on experience with the Advantest 93K ATE platform including test program development for wafer sort and final test
• Strong technical foundation in high-speed SerDes protocols (PCIe, Ethernet, CXL) and/or memory interfaces (DDR5/LPDDR5)
• Experience defining and executing standards-based qualification at product and package level
• Demonstrated track record delivering semiconductor products to high-volume production with quality
• Strong data analysis skills and experience with statistical tools (JMP, Spotfire, or equivalent)
• Digital and analog circuit-level understanding for DUT characterization and debug

Preferred Qualifications

• Master's degree in Electrical Engineering or Computer Engineering
• Experience working with silicon validation teams to correlate device performance with production requirements
• Firmware development experience in C/C , scripting in Python, or equivalent programming skills
• Experience with advanced process nodes (5nm and below)
• Proven success partnering with OSATs in a fabless semiconductor operating model
• Prior experience in a high-growth company shipping products to hyperscaler customers

The salary range for this position is $187,200 to $260,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ and non-binary people, veterans, parents, and individuals with disabilities.