Director Digital Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com.

Job Description  

We are seeking a Director of Digital Design Engineering to lead the microarchitecture, RTL implementation, and front-end development of high-performance connectivity solutions for next-generation network controllers. The ideal candidate has deep expertise in front-end ASIC design, strong leadership experience, and a solid understanding of communication and interface standards such as PCIe, Ethernet, UALink.This role requires on-site presence.

Basic Qualifications:  

• Bachelor’s degree in Electrical or Computer Engineering required; Master’s degree preferred.
• 12 years of experience developing or supporting complex SoC/silicon products for server, storage, or networking applications.
• 5 years of technical leadership or engineering management experience.
• Strong professional presence with the ability to manage multiple priorities, prepare for and lead customer discussions, and operate independently with minimal supervision.
• Entrepreneurial, open-minded, and action-oriented mindset with a strong customer focus.
• Authorized to work in the U.S. and able to start immediately.

Required Experience:  

• Hands-on experience and strong working knowledge of Ethernet or UALink.
• Solid understanding of packet-based switching architectures and network protocol processing.
• Proven experience with switch fabrics, crossbar architecture, and high-speed memory subsystems.
• Familiarity with high-speed interconnect protocols such as Ethernet, UALink, Infinity Fabric, NVLink, or HyperTransport.
• Strong front-end design expertise including architecture, RTL development, simulation, synthesis, timing closure, GLS, and DFT.
• Demonstrated ownership of full-chip or block-level development from architecture through GDS, delivering multiple complex designs into production, working closely with both hardware and software teams.
• Experience with Cadence and/or Synopsys digital design and DFT tool flows.
• Knowledge of DFT methodologies, including stuck-at and transition fault scan insertion.
• Expertise in silicon bring-up, performance tuning, and lab-based debug using equipment such as logic analyzers, scopes, protocol analyzers, and high-speed test setups.
• Experience working with advanced technology nodes (5nm or below).

Preferred Experience:  

• Proficiency in scripting languages such as Python or equivalent.
• Experience developing or supporting PCIe, Ethernet, or DDR-based products; familiarity with security-related standards.
• Background in developing ASIC design methodologies and driving methodology adoption across teams. 

The base salary range is $218,500 USD – $260,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions. This position can be hired as a Senior Manager Level or Director Level. 

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ and non-binary people, veterans, parents, and individuals with disabilities.