Senior Digital Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com.

Job Description

Astera Labs is seeking a Digital Design Engineer to join our ASIC IP & Methodology team. In this role, you will contribute to the front-end design and development of high-performance digital IP blocks, including RTL design, synthesis, and verification. You will gain hands-on ownership of block-level design, integration, and debug, while working closely with senior architects and methodology experts to advance your skills. This position is ideal for engineers who want to expand into full-chip ownership and methodology, while immediately contributing to next-generation connectivity products for AI, Cloud, and Data Center markets.

Key Responsibilities

• Develop micro-architecture and RTL implementation for digital IP blocks.
• Perform synthesis, lint, CDC, and static timing analysis.
• Own block-level design and verification (simulation, UVM-based flows).
• Integrate IP blocks into larger ASIC systems and collaborate across teams to ensure timing and functionality.
• Support silicon bring-up and debug of first silicon.
• Contribute to design methodology improvements, automation, and best practices.
• Work closely with senior architects to grow toward full-chip design ownership.
  
  

Basic Qualifications

• B.S. in Electrical or Computer Engineering (M.S. preferred).
• 5 years of ASIC or SoC design experience in Server, Storage, Networking, or related domains.
• Proficiency in RTL design, synthesis, and timing closure.
• Familiarity with high-speed protocols (PCIe Gen3 , Ethernet, DDR, NVMe, USB, etc.).
• Hands-on experience with EDA toolchains (Synopsys, Cadence).
• Exposure to DFT concepts (scan insertion, testability).
• Familiarity with UVM-based DV and block-level verification.
• Experience with deep sub-micron CMOS nodes (≤28nm).
  
  

Preferred Qualifications

• Prior involvement in silicon bring-up and debug.
• Scripting experience (Python, Perl, TCL, or equivalent).
• Understanding of system-level integration (SoC/ASIC).
• Background in PCIe or Ethernet switch/retimer products.
• Strong team-oriented mindset, with a drive to learn and take on increasing ownership.
  
  

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ and non-binary people, veterans, parents, and individuals with disabilities.