Optical Chip Validation Engineer, Senior Principal

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

We are seeking an experienced Optical Chip (EIC/PIC) Validation Engineer at the Senior Principal level to lead the validation, characterization, and qualification of advanced photonic integrated circuits (PICs) closely integrated with electronic integrated circuits (EICs) multiple optical configurations.

This high-impact role focuses on ensuring the performance, reliability, and manufacturability of next-generation optical engines for high-speed data center, AI/ML, and telecom applications. The ideal candidate has deep expertise in electro-optical testing, system-level validation, and multiple optical integration challenges.

Key Responsibilities

• Lead end-to-end validation and characterization of Optical Engines integrating EIC and PIC in co-packaged and near-packaged optics architectures.
• Develop comprehensive test plans, methodologies, and automation frameworks for optical, electrical, and electro-optical performance metrics (e.g., BER, eye diagrams, insertion loss, extinction ratio, receiver sensitivity, transmitter power).
• Perform detailed characterization of key building blocks: modulators, photodetectors, lasers, waveguides, couplers, and high-speed EIC/PIC interfaces.
• Validate co-packaged optics performance including high-speed electrical interfaces (SerDes, UCIe), thermal management, signal integrity, power integrity, and optical coupling efficiency.
• Design and implement test setups for wafer-level, package-level, and system-level testing, including active alignment, thermal cycling, reliability stress, and environmental qualification.
• Collaborate closely with PIC Design, EIC Design, Packaging, Test Engineering, and Manufacturing teams to close design-for-test (DfT) and design-for-manufacturability (DfM) gaps.
• Analyze large datasets from validation runs, perform failure analysis, root cause investigation, and drive corrective actions.
• Support bring-up and debug of silicon photonics prototypes and optical modules.
• Define and execute qualification plans per industry standards (Telcordia, GR-468, JEDEC, etc.).
• Mentor junior engineers and contribute to intellectual property through patents and technical publications.
  
  

Qualifications & Requirements

• Master’s or PhD in Electrical Engineering, Optical Engineering, Photonics, Physics, or related field.
• 8 years (Senior) to 12 years (Principal) of hands-on experience in silicon photonics or optical transceiver validation.
• Strong experience with EIC/PIC co-design validation, multiple Optical Configurations.
• Expertise in high-speed optical and electrical testing: BER testers, sampling oscilloscopes, VNAs, spectrum analyzers, tunable lasers, optical power meters, and automated test equipment.
• Proficiency with photonic test automation (Python, LabVIEW, or equivalent) and data analysis tools (JMP, MATLAB, Python/Pandas).
• Deep understanding of optical coupling, thermal effects in 2.5D/3D packaging, and high-speed signal integrity challenges in CPO systems.
• Familiarity with industry standards for reliability and qualification of photonic components.
• Excellent problem-solving, communication, and cross-functional collaboration skills.
  
  

Preferred Qualifications

• Direct experience validating production-grade silicon photonics modules for hyperscale data centers or AI clusters.
• Knowledge of advanced packaging technologies (2.5D, 3D stacking, hybrid bonding, interposers).
• Experience with high-speed SerDes (112G/224G PAM4) and optical I/O chiplets.
• Track record of shipping high-volume optical products.
• Publications or patents in silicon photonics or co-packaged optics.
  
  

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ and non-binary people, veterans, parents, and individuals with disabilities.