What are the responsibilities and job description for the Senior FPGA Engineer (DOD cleared) position at Associates Systems LLC?
All Qualified candidates will be responded to in 24 hours or less
Interim Secret required prior to start
Employment type: Full Time W-2 or Contract
Rate: open to Negotiation
Benefits: including Health, Dental Vision, PTO, Holidays, 401K,etc
Senior FPGA Engineer
Location: Tucson, AZ
Schedule: On-Site
Clearance: Secret clearance or higher required prior to start
Role Summary
Seeking a senior-level FPGA Engineer to support the design, development, verification, and integration of production-quality FPGA solutions for advanced defense systems. This role covers the full FPGA lifecycle from requirements and architecture through VHDL coding, simulation, place-and-route, integration, debug, and production release support.
Key Responsibilities
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Develop and verify FPGA designs using VHDL.
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Support FPGA architectures for system-level applications.
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Translate system-level requirements into FPGA requirements.
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Perform simulation, synthesis, place-and-route, timing closure, integration, and debug.
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Work with circuit card designers and systems engineers to define interfaces and design requirements.
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Support FPGA designs involving RF/EO DSP, controls, data links, embedded processing, processor interfaces, and gigabit serial interfaces.
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Create technical documentation, including requirements, verification plans, and user guides.
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Support internal and external technical reviews as needed.
Required Skills
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8 years of FPGA engineering experience.
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VHDL coding and digital design experience.
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Experience with Xilinx, Altera, or Microsemi FPGA devices and tool flows.
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Hands-on FPGA integration and debug experience.
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Experience delivering FPGA solutions into system-level applications.
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Ability to support FPGA work from requirements definition through integration and test.
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Secret clearance or higher required prior to start.
Preferred Skills
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Radar or image processing experience.
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Embedded systems experience using ARM, MicroBlaze, or Nios processors.
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Experience with gigabit serial interfaces or multi-gigabit transceivers.
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SystemVerilog / UVM verification experience.
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Experience with emulation platforms such as Veloce.
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Strong technical documentation and review support experience.
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