Principal Power Modeling System Architect

As a Principal Power Modeling System Architect you would be shaping the architecture and development processes across Arm's latest subsystem and platform architectures, impacting Arm IP, subsystems, platform architecture and system IP

The Central Technology - Systems team is a diverse set of motivated engineers covering all aspects of system architecture. We work in partnership with the engineering teams to define architectures for Arm's Client, Infrastructure, Automotive and IoT systems.

Do you have rich experience in SoC development, with exposure to feature enablement, IP development, post-silicon lab work, firmware, power execution, and power modeling and are passionate about testing assumptions, and making quantitative decisions that deliver outstanding power and performance? If so, you have the opportunity to join a small team who share a passion for extracting the maximum performance and power efficiency from the very latest process and packaging technologies!

Responsibilities:

• Drive a quantitative wholistic power-modeling process to facilitate vital development processes, including architecture, physical implementation, firmware, package PDN, PCB PDN, and software power management for cutting edge products.
• Build consensus and knowledge across teams for complex multi-functional topics, to meet key performance system level indicators.
• Collaborate on the development of new cross-team initiatives, required to deliver successful products.
• Create internal specifications and partner/customer documentation to drive solution development.
• Learn where to focus effort and develop teamwork, in areas that will return outsized benefits.

Required Skills and Experience :

• B.Sc. in Electronic, Electrical or Computer Engineering. Other degrees will also be considered with relevant experience.
• 7 years experience in power management and/or power analysis for complex SoCs or IPs, preferable involving CPUs and/or GPUs.
• Proven experience estimating, modeling and evaluating workload power & thermal characteristics, before and after tapeout.
• Experience with ASIC power state definition and optimization techniques, such as power gating, clock gating, dynamic voltage and frequency scaling (DVFS) and aging mitigations.

Personal Attributes:

• Creative, multifaceted thinker, open minded with strong problem-solving skills.
• Fast learner of new technologies and concepts.
• Ability to work in a collaborative, diverse and inclusive environment, across time zones.
• Excellent verbal, written and interpersonal communication skills.

"Nice To Have" Skills and Experience :

• Masters or PhD in Electronic, Electrical or Computer Engineering.
• Experience with Arm processors, CPU architecture, interconnect and SoC subsystems.
• Understanding the key use cases, design constraints and workloads in a modern smartphone Application Processor SoCs, laptops or Infrastructure systems.
• Experience with SoC clock architectures.
• Understanding of timing and Vt mix.
• Knowledge of pre and post-silicon development processes.

In Return:

We offer a competitive reward package including annual bonus, RSUs and healthcare support. As well as other benefits, such as an on-site gym, and social events that are organized within the company!

We are offering a hybrid approach to home and office working to provide an adaptable experience for all employees. We expect some working time to be spent in office, to promote a strong collaborative environment with good team integration, but are accommodating to different home working requirements.

#LI-MS1