What are the responsibilities and job description for the Senior Physical Design Engineer position at Aril Inc.?
Senior Physical Design Engineer
About Aril
We are a stealth mode startup company in Silicon Valley working on high performance low power RISC-V processor design. We have an experienced microprocessor design team and are looking for highly motivated individuals who are interested in working on high end processor design in a small team environment.
Job Description
As a senior physical design engineer you will be responsible for rtl->gds2 execution of full chip tape outs. You will generate the top level floorplan, integrate IPs, develop power and clock plans and execute the silicon implementation through PDV.
You should expect to interact with the foundry and package assembly vendors to ensure compliance and successful product manufacturing. PDV requirements must be communicated to internal IP development teams to ensure top level integration.
Responsibilities:
- Floorplan high performance multi-processor SOC
- Develop power infrastructure for multi-power domain distribution
- Develop and implement high speed SOC level clocking scheme along with CTS flows for hierarchical blocks
- Work with IP teams to ensure validity, completeness and usability of developed collateral (LIB/LEF etc.)
- Complete all SOC level signoff checks and generate final GDS2 for delivery to foundry.
Requirements:
- BS EE 10 years experience in physical design
- Tape out experience in advance technology node (5nm or below)
- Experience with CTS of high speed clocks (3GHz )
- Experience with multiple power domain designs (UPF/CPF)
- Good coding skills, experience developing scripts for use by others
- Programing languages: TCL
- Tools: Innovus, Pegasus/ICV, Primetime/Tempus, Voltus
- Excellent team player, innovative and self-driven with good communication skills
- Enjoy working in a small team environment in a startup company.