What are the responsibilities and job description for the DFT (Design for Test) Engineer position at APR Consulting?
An aerospace client is looking for a DFT (Design for Test) Engineer to join our highly qualified, diverse individuals as part of our client’s ASIC design team.
Location: Harrisburg, PA 17101 (Remote)
Position: DFT (Design for Test) Engineer
Pay Rate: $62.99 - $81.38/hr. on W2 (DOE)
Duration: 12 months or longer
Schedule: 9x80 A
Shift: 1st Shift
Responsibilities:
Location: Harrisburg, PA 17101 (Remote)
Position: DFT (Design for Test) Engineer
Pay Rate: $62.99 - $81.38/hr. on W2 (DOE)
Duration: 12 months or longer
Schedule: 9x80 A
Shift: 1st Shift
Responsibilities:
- Responsible for DFT (Design for Testability) aspects of ASIC Design thorough understanding of digital design concepts
- Adhering to Northrop Grumman ASIC development process.
- Knowledgeable in VHDL, Verilog or System Verilog RTL coding and highly proficient in DFT methodologies.
- Responsible for operating in a team environment and collaborating across the different teams as required to accomplish the goals.
- Technical environment: Design using Linux platforms.
- Typical day look like: Develop DFT architecture, provide detailed documentation and work with wider Digital designers to drive the implementation.
Qualifications:- U.S. Citizenship required.
- Bachelor's degree in Electrical or Computer Engineering with 8 years’ experience.
- Bachelor’s degree with 8 years of experience, a Master’s degree with 6 years of experience
- Experience in full product life cycle of ASIC Design.
- Experience with Cadence and/or Mentor test insertion and ATPG tools.
- Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTAG).
- Experience with memory BIST and logic BIST.
- Experience generating test patterns and analyzing and debugging test failures.
- Experience working with test engineers to implement ATPG vectors on tester hardware.
- Proficiency in HDL (VHDL/Verilog/System Verilog) and scripting languages such as Tcl, Python or Perl.
- Effective communication and presentation skills and high proficiency in technical problem solving.
Preferred Qualifications- Master's Degree in Electrical or Computer Engineering
- Expertise of using Cadence Modus DFT tools
- Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus
About our client:
Our client is a world leader and premier innovator in aerospace, with over 100,000 top talent employees providing the most advanced products and technologies in the industry. With numerous awards and recognitions, they offer continuous growth, learning, and development for their employees.
About APR:
Since 1980 APR Consulting, Inc. has provided professional recruiting and contingent workforce solutions to a diverse mix of clients, industries, and skill sets nationwide.
We are an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law.
Don't miss out on this amazing opportunity! If you feel your experience is the match for this position please apply today and join our team. We look forward to working with you!
#SLA
- Master's Degree in Electrical or Computer Engineering
- U.S. Citizenship required.
- Technical environment: Design using Linux platforms.
Salary : $63 - $81