What are the responsibilities and job description for the SerDes System Validation Engineer position at Apple?
We are looking for a SerDes System Validation Engineer to lead system validation of mixed-signal SerDes IP. In this highly visible role, you will actively work within Analog-Mixed/Signal design team and participate in validation and debug of embedded circuits; collaborating with many teams to enable the world’s premiere products. You will closely work with a hard-working group of Analog-Mixed/Signal designers working diligently to deliver hard IPs to Apple’s products while exceeding the highest expectations of quality, innovation and efficiency.
At Apple, we work every day to craft products that enrich people’s lives. In doing so, we face exciting challenges driven by the increasing complexity of SoC and PHY design. If you have strong technical fundamentals and a proven record of tackling complex problems—fueled by curiosity, a passion for learning, and a desire to enhance the impact of your work—we’d love to hear from you.
If you thrive on understanding the bigger picture while diving deep into the details to innovate and find elegant solutions. You enjoy collaborating with diverse teams to achieve extraordinary results, maintaining a strong team spirit even when facing tough challenges. Most importantly, you care about society and demonstrate leadership through your commitment to meaningful causes.
We have an opportunity for a forward-thinking and especially hardworking system validation engineer with strong background in high-speed serial links. As a member of our dynamic team, you will have the rare and rewarding opportunity to work on upcoming products that will surprise and delight millions of Apple’s customers every day.
And all of this while enjoying a great culture where you own your career.
Ownership of SerDes system bring-up, validation and debug. This will involve a SerDes bring up in system environment, verifying basic operations, analyzing robustness and margins in system.
Work with design teams to understand the architecture and define DFT needs to help enhance testability and first-time silicon success.
Be involved in mixed-signal verification tasks to better understand the SerDes operation and interaction with higher level control logic.
Minimum Qualifications:
Minimum requirement of a bachelors degree.
Preferred Qualifications:
Able to think outside of the box and come up with creative solutions for system validation.
Knowledge of system level considerations e.g. ESD requirements.
Very knowledgeable about and experienced with common high-speed SerDes protocols (e.g., PCIe, USB, UCIe, OIF, etc.).
Experience with system bring-up of high-speed serial links, lab testing, and defining equipment needs.
Very knowledgeable in scripting (e.g. python, C, Matlab) for automation of validation efforts.
Experience with system level S/W setup.
Experience in mixed-signal circuit pre-silicon verification and ability to closely work with circuit design team.
Knowledge of DFT to aid in the system validation.
Experience in leading mixed-signal SerDes system validation.
Experience with silicon bring-up, debug and production ramp.
Knowledge of SerDes design and architecture including CDR and equalization.
Knowledge of with Tx/Rx equalization techniques and adaptation.
Knowledge of link jitter budget for high-speed serial links and key block level requirements.
Knowledge of ADC based links and equalization techniques.
Familiarity with PCB design and specifications.
Strong communication, teamwork and problem-solving skills.
Proven track record of delivering under difficult debug and validation scenarios.